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| Number | Title | Issue Date |
| 7385236 | BiFET semiconductor device having vertically integrated FET and HBT The invention provides a BiFET semiconductor device vertically integrating a FET and a HBT on the same substrate. The BiFET semiconductor device comprises a HBT structure, a high-resistivity structure, and a FET structure, sequentially formed in this order from bott... | 06/10/2008 |
| 7307328 | Semiconductor device with temperature sensor A semiconductor device is disclosed. In one embodiment the semiconductor device includes a semiconductor body of which is integrated a temperature sensor for measuring the temperature prevailing in the semiconductor body. The temperature sensor has a MOS transistor ... | 12/11/2007 |
| 7285454 | Bipolar transistors with low base resistance for CMOS integrated circuits Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the... | 10/23/2007 |
| 7285830 | Lateral bipolar junction transistor in CMOS flow An improved lateral bipolar junction transistor and a method of forming such a lateral bipolar transistor without added mask in CMOS flow on a p-substrate are disclosed. The CMOS flow includes patterning and n-well implants; pattern and implant pocket implants for c... | 10/23/2007 |
| 7271070 | Method for producing transistors The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is de... | 09/18/2007 |
| 7262472 | Semiconductor device having stress and its manufacture method A semiconductor device has: active regions including a p-type active region; an insulated gate electrode structure formed on each of the active regions, and having a gate insulating film and a gate electrode formed thereon; side wall spacers formed on side walls of ... | 08/28/2007 |
| 7205657 | Complimentary lateral nitride transistors A semiconductor device which includes a laterally extending stack of laterally adjacent conductive semiconductor regions formed over a support surface of a substrate, and a method for fabricating the device. ... | 04/17/2007 |
| 7198998 | Method of manufacturing bipolar-complementary metal oxide semiconductor A method of manufacturing a bipolar-complementary metal oxide semiconductor (BiCMOS) is provided. A gate in a CMOS area and a conductive layer pattern defining an opening, which opens an active region in a bipolar transistor area, are simultaneously formed by patter... | 04/03/2007 |
| 7095094 | Multiple doping level bipolar junctions transistors and method for forming A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A... | 08/22/2006 |
| 7015519 | Structures and methods for fabricating vertically integrated HBT/FET device Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for f... | 03/21/2006 |
| 6703685 | Super self-aligned collector device for mono-and hetero bipolar junction transistors The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is dispo... | 03/09/2004 |
| 6700144 | Semiconductor device and method for manufacturing the same A semiconductor device includes the following: a semiconductor substrate of a first conduction type; an intrinsic semiconductor layer of the first conduction type formed on the semiconductor substrate; a first semiconductor layer of a second conduction ty... | 03/02/2004 |
| 6690212 | Inductive load driving circuit An inductive load driving circuit includes a switching transistor and a guardring. The switching transistor is connected between an output terminal and a power supply potential point. The guardring is an N-type semiconductor region provided for the switch... | 02/10/2004 |
| 6667202 | Semiconductor device and method for making the same A semiconductor device which has: a bipolar transistor having a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the su... | 12/23/2003 |
| 6667521 | Bipolar transistor with raised extrinsic base fabricated in an integrated BiCMOS circuit A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is ... | 12/23/2003 |
| 6649983 | Vertical bipolar transistor formed using CMOS processes A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect device. The implantation steps form an n-well, a p-well region, a pocket base region and an emitter... | 11/18/2003 |
| 6646311 | Vertical bipolar transistor formed using CMOS processes A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect device. The implantation steps form an n-well, a channel stop p-well region and emitter region whic... | 11/11/2003 |
| 6639294 | Semiconductor device having a device formation region protected from a counterelectromotive force A semiconductor device includes an epitaxial layer formed on a P type silicon substrate; a P+ diffusion layer for dividing the epitaxial layer into an N- epi layer, which constitutes a device formation region, and an N- epi layer, which constitutes an inv... | 10/28/2003 |
| 6638806 | Semiconductor device and method of fabricating the same A collector region is formed on a semiconductor substrate. An emitter electrode, an external base electrode and a gate electrode are formed on the semiconductor substrate. The position of the interface between the gate electrode and the semiconductor subs... | 10/28/2003 |
| 6633063 | Low voltage transient voltage suppressor and method of making A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with r... | 10/14/2003 |
| 6630377 | Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reach... | 10/07/2003 |
| 6620653 | Semiconductor device and method of manufacturing the same A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is ... | 09/16/2003 |
| 6617647 | Insulated gate semiconductor device and method of manufacturing the same Dot-pattern-like impurity regions 104 are artificially and locally formed on a channel forming region 103. The impurity regions 104 restrain the expansion of a drain side depletion layer toward the channel forming region 103 to prevent the short channel e... | 09/09/2003 |
| 6607960 | Bipolar transistor manufacturing method A method of manufacturing a bipolar transistor in a P-type substrate, including the steps of forming in the substrate a first N-type area; forming by epitaxy a first silicon layer; forming in this first layer, and substantially above the first area a seco... | 08/19/2003 |
| 6586780 | Semiconductor device for supplying output voltage according to high power supply voltage A semiconductor device includes a p type semiconductor substrate, a first n type region formed at the semiconductor substrate, a first n channel DMOS transistor formed in the first n type region, a second n type region formed at the semiconductor substrat... | 07/01/2003 |
| 6576535 | Carbon doped epitaxial layer for high speed CB-CMOS A method for fabricating a high speed complementary bipolar/CMOS device is disclosed which enables the forming of a silicon epitaxial layer in a PNP transistor having carbon incorporated therein to suppress boron up-diffusion from lower heavily boron-dope... | 06/10/2003 |
| 6570229 | Semiconductor device An insulated gate N-channel field effect transistor has a P-type semiconductor substrate, an N-type epitaxial layer disposed on the P-type semiconductor substrate, and a gate insulating film disposed on the N-type epitaxial layer. An N-type high concentra... | 05/27/2003 |
| 6570242 | Bipolar transistor with high breakdown voltage collector A transistor that includes a doped buried region 320 within a semiconductor body 300, 340. The doped buried region includes a portion having a first thickness 348 and a second thickness, the first thickness being less than the second thickness. In one emb... | 05/27/2003 |
| 6569744 | Method of converting a metal oxide semiconductor transistor into a bipolar transistor The present invention provides a method of manufacturing a bipolar transistor. The method includes producing an opening in a dielectric layer located over a substrate and forming a collector in the substrate by implanting a first dopant through the openin... | 05/27/2003 |
| 6559505 | Power integrated circuit with vertical current flow and related manufacturing process Integrated circuit including a power component with vertical current flow and at least one low or medium voltage component, the at least one low or medium voltage component formed in a first semiconductor layer separated from a second semiconductor layer ... | 05/06/2003 |
| 6555871 | Flash memory device having a bipolar transistor formed integral thereto and a method of manufacture therefor The present invention provides a bipolar transistor for use in increasing a speed of a flash memory cell having a source region and a drain region and first and second complementary tubs. In one embodiment, a base for the bipolar transistor is located in ... | 04/29/2003 |
| 6537887 | Integrated circuit fabrication An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor de... | 03/25/2003 |
| 6528826 | Depletion type MOS semiconductor device and MOS power IC A depletion type MOS semiconductor device is provided which includes a p- well region formed in a surface layer of an n- drift layer, an n+ emitter region formed in a surface layer of the p31 well region, an n | 03/04/2003 |
| 6501152 | Advanced lateral PNP by implant negation A lateral NPN transistor (LPNP) (102) having the lightly doped drain extension implant blocked from the emitter region (118) but not the collector region (120). Accordingly, the emitter region (118) has a more abrupt junction for high emitter injection ef... | 12/31/2002 |
| 6501330 | Signal processing semiconductor integrated circuit device A semiconductor integrated circuit comprising a first circuit block including an oscillation circuit considered to be a noise generator and a second circuit block including circuits considered to be easily affected by a noise generated by the oscillation ... | 12/31/2002 |
| 6492238 | Bipolar transistor with raised extrinsic base fabricated in an integrated BiCMOS circuit A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is ... | 12/10/2002 |
| 6489665 | Lateral bipolar transistor A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral ... | 12/03/2002 |
| 6476450 | BICMOS semiconductor integrated circuit device and fabrication process thereof Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate typ... | 11/05/2002 |
| 6472753 | BICMOS semiconductor integrated circuit device and fabrication process thereof Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate typ... | 10/29/2002 |
| 6469362 | High-gain pnp bipolar junction transistor in a CMOS device and method for forming the same An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipol... | 10/22/2002 |
