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| Number | Title | Issue Date |
| 7417330 | Semiconductor device packaged into chip size and manufacturing method thereof A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semicon... | 08/26/2008 |
| 7303934 | Method for manufacturing a micro-electromechanical device and micro-electromechanical device obtained therewith The invention relates to a method of manufacturing a micro-electromechanical device (10), in which are consecutively deposited on a substrate (1) a first electroconductive layer (2) in which an electrode (2A) is formed, a first electroins... | 12/04/2007 |
| 7129576 | Structure and method of making capped chips including vertical interconnects having stud bumps engaged to surfaces of said caps A capped chip is provided which includes a chip and a cap member, the chip having a front surface and a plurality of bond pads exposed at the front surface, the cap member having a bottom surface facing the front surface of the chip and having a top surface opposite... | 10/31/2006 |
| 7095123 | Sensor semiconductor package, provided with an insert, and method for making same A semiconductor package includes a mounting and electrical connection plate, and a semiconductor component having front and rear surfaces and including a sensor. The rear surface of the semiconductor component is attached to the mounting and electrical connection pl... | 08/22/2006 |
| 7088007 | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument A semiconductor chip is adhered to a substrate by using an adhesive, and a sealant is provided around the semiconductor chip, on a surface of the substrate on which the semiconductor chip is mounted. The adhesive is provided to reach a side surface of the semiconduc... | 08/08/2006 |
| 6693029 | Method of forming an insulative substrate having conductive filled vias A method for manufacturing a substrate, including adhering an adhesive layer to an organic insulation substrate to form a first part; forming a via hole in the first part such that the via hole penetrates the first part; forming a conductive metal film so... | 02/17/2004 |
| 6661089 | Semiconductor package which has no resinous flash formed on lead frame and method for manufacturing the same Disclosed is a semiconductor package which has no resinous flash formed on a lead frame and its manufacturing method. The method includes the steps of preparing a lead frame having a first surface and a second surface, attaching an adhesive tape capable o... | 12/09/2003 |
| 6639315 | Semiconductor device and mounted semiconductor device structure A small semiconductor device which can be fabricated at the wafer level has high reliability of external terminals with respect to distortion caused by differential thermal expansion between a semiconductor element of the device and a printed circuit boar... | 10/28/2003 |
| 6624504 | Semiconductor device and method for manufacturing the same A semiconductor apparatus includes a semiconductor device having circuit electrodes aligned centrally of the semiconductor apparatus. A first electrically insulating layer is formed on said semiconductor device with said circuit electrodes being exposed f... | 09/23/2003 |
| 6608372 | Surface mountable chip type semiconductor device and manufacturing method A surface mountable chip type semiconductor device comprises: first and second conductive land areas which are formed on an insulating substrate and which are electrically coupled with each other; a conductive post formed on the first conductive land area... | 08/19/2003 |
| 6586275 | Wafer level package and method for manufacturing the same A thermal-stress-absorbing interface structure between a semiconductor integrated circuit chip and a surface-mount structure and a method for manufacturing the same. The thermal-stress-absorbing interface structure comprises an elongated conductive-bump p... | 07/01/2003 |
| 6562663 | Microelectronic assembly with die support and method A microelectronic assembly includes a substrate having a plurality of bond pads disposed on a substantially planar die attach surface and an integrated circuit die having a die face and a plurality of bond pads of the die face. The die is provided with a ... | 05/13/2003 |
| 6544879 | Insitu radiation protection of integrated circuits Methods for manufacturing microchips are provided. A plurality of alternating metallic wiring-layers and non-metallic layers, terminating with a metallic wiring-layer, are formed on a wafer. A plurality of vias is formed for electrically interconnecting v... | 04/08/2003 |
| 6528769 | Connection of a junction to an electrical conductor track on a plate A connection of an electrical terminal 13 to a conductor track 5 applied to a glass or glass ceramic plate 1 is to be resistant to temperature change and traction and conductive. For this purpose an electrically conductive connecting element 11 is ultraso... | 03/04/2003 |
| 6521980 | Controlling packaging encapsulant leakage An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation a... | 02/18/2003 |
| 6518675 | Wafer level package and method for manufacturing the same A thermal-stress-absorbing interface structure between a semiconductor integrated circuit chip and a surface-mount structure, and a method for manufacturing the same. The thermal-stress-absorbing interface structure comprises an elongated conductive-bump ... | 02/11/2003 |
| 6504256 | Insitu radiation protection of integrated circuits A microchip having a passivation layer on an electrically active surface; a multitude of electrically conducting protuberances for electrically coupling the active surface to a substrate; a layer on the passivation layer for protecting against electromagn... | 01/07/2003 |
| 6484708 | Resin sealed electronic device Durability and lifetime of a resin sealed electronic device is improved by reducing thermal stresses acting on the power element and the parts mounting on the board. A power element of which the protective film on the power element is coated with a polyim... | 11/26/2002 |
| 6476482 | Chip-size integrated circuit package having slits formed in an insulator tape In a chip-size package, an insulator tape is formed with a conductive wire having a wider section which is greater in width than other sections of the wire and a conductive bump connected to the wider section of the wire. The insulator tape is further for... | 11/05/2002 |
| 6469397 | Resin encapsulated electrode structure of a semiconductor device, mounted semiconductor devices, and semiconductor wafer including multiple electrode structures A semiconductor integrated circuit device includes a semiconductor substrate having a first surface and including an electrode on the first surface of the semiconductor substrate; a surface protecting film covering the first surface of the semiconductor s... | 10/22/2002 |
| 6441473 | Flip chip semiconductor device An improved flip chip assembly is disclosed of the type where a semiconductor chip having a certain thermal expansion coefficient is directly mounted via solder bumps on the metallization pattern of a circuit substrate having a different thermal expansion... | 08/27/2002 |
| 6429047 | Semiconductor package which has no resinous flash formed on lead frame and method for manufacturing the same Disclosed is a semiconductor package which has no resinous flash formed on lead frame and its manufacturing method. The method includes the steps of preparing a lead frame having a first surface and a second surface, attaching an adhensive tape capable of... | 08/06/2002 |
| 6429530 | Miniaturized chip scale ball grid array semiconductor package A semiconductor package arrangement and, more particularly, a light weight and miniaturized electronic package or module, wherein the dimensions between an integrated circuit comprising a semiconductor chip and those of a chip carrier have been optimized ... | 08/06/2002 |
| 6426545 | Integrated circuit structures and methods employing a low modulus high elongation photodielectric Structures and methods are provided for absorbing stress between a first electrical structure and a second electrical structure connected together, wherein the first and second structures have different coefficients of thermal expansion. A dielectric mate... | 07/30/2002 |
| 6412786 | Die seal ring The present invention proposes a die seal ring. The provided die seal ring is formed on a substrate and is used to encompass a die by locating between the die and adjacent scribe lines. Moreover, the provided die seal ring comprises a plurality of dielect... | 07/02/2002 |
| 6395579 | Controlling packaging encapsulant leakage An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation a... | 05/28/2002 |
| 6379988 | Pre-release plastic packaging of MEMS and IMEMS devices A method is disclosed for pre-release plastic packaging of MEMS and IMEMS devices. The method can include encapsulating the MEMS device in a transfer molded plastic package. Next, a perforation can be made in the package to provide access to the MEMS elem... | 04/30/2002 |
| 6373128 | Semiconductor assemblies with reinforced peripheral regions A semiconductor chip assembly with a compliant layer overlying the chip and a flexible dielectric layer overlying the compliant layer. Connecting terminals are provided on the dielectric layer for connection to a larger substrate. The connecting terminals... | 04/16/2002 |
| 6351031 | Semiconductor device and method for manufacturing substrate of the same A semiconductor device includes a multi-flexible substrate and semiconductor chips mounted thereon. The multi-flexible substrate is configured such that organic insulation substrate layers and filmy adhesive layers are alternatively stacked together and w... | 02/26/2002 |
| 6331452 | Method of fabricating integrated circuit package with opening allowing access to die An I.C. die is mounted on a base of an open-tooled package. The open-tooled package comprises a substrate, the substrate having a base, a plurality of sidewalls, and a plurality of leads extending through at least one of the sidewalls. A cavity is formed ... | 12/18/2001 |
| 6284554 | Process for manufacturing a flip-chip integrated circuit A method of producing a packaged semiconductor chip including hardened resin packaging and a polished electrode includes producing an electrode on a first surface of a semiconductor substrate; depositing a glass layer on the first surface of the semicondu... | 09/04/2001 |
| 6210992 | Controlling packaging encapsulant leakage An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation a... | 04/03/2001 |
| 6204566 | Resin encapsulated electrode structure of a semiconductor device, mounted semiconductor devices, and semiconductor wafer including multiple electrode structures A semiconductor integrated circuit device includes a semiconductor substrate having a first surface and including electrodes on the first surface of the semiconductor substrate; a glass coating film covering the first surface of the semiconductor substrat... | 03/20/2001 |
| 6175162 | Semiconductor wafer having a bottom surface protective coating Disclosed is a packaged integrated circuit device. The device includes a die having a plurality of electrical contacts on a first surface of the die and a protective film adhered directly to a back surface of the die, the protective film being thick enoug... | 01/16/2001 |
| 6163076 | Stacked structure of semiconductor package A stacked structure of a semiconductor package mainly comprises a first chip, a second chip, a substrate and a lead frame. The first chip and the second chip are attached on the surface of the substrate by a plurality of solder bumps by means of flipchip ... | 12/19/2000 |
| 6159869 | Method of making a circuit including a corral for containing a protective coating A circuit including an active area, at least one bond pad and a corral formed on the circuit between the active area and the bond pad. A method including providing a circuit with an active area and at least one bond pad and forming a corral on the circuit... | 12/12/2000 |
| 6087586 | Chip scale package A chip scale package for packaging an IC chip includes a package frame displaced from the side and bottom surfaces of the IC chip by a predetermined gap and a pair of leads symmetrically extending in opposite directions. Each lead has an inner lead portio... | 07/11/2000 |
| 6060779 | Resin sealed ceramic package and semiconductor device A resin sealing ceramic package 10 for resin sealing of a semiconductor element 14 mounted in a cavity 16, the ceramic package having a bleed-out-preventing metal pattern 24, to prevent bleed-out of a sealing resin filled in the cavity 16 from out of the ... | 05/09/2000 |
| 6043100 | Chip on tape die reframe process A die is unpackaged from a Chip on Tape by grinding off molding compound from an upper surface of the COT until the COT's leads are evenly exposed across the upper surface, selectively etching out the leads using the remaining molding compound as a mask, ... | 03/28/2000 |
| 6023094 | Semiconductor wafer having a bottom surface protective coating Disclosed is a packaged integrated circuit device. The device includes a die having a plurality of electrical contacts on a first surface of the die and a protective film adhered directly to a back surface of the die, the protective film being thick enoug... | 02/08/2000 |
