Celebrity Inventors
Mark Twain (Samuel L. Clemens) received Patent No. 121,992 for "An Improvement in Adjustable and Detachable Straps for Garments." He later received two more patents: one for a self-pasting scrapbook and one for a game to help players remember important historical dates.
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| Number | Title | Issue Date |
| 7435993 | High temperature, high voltage SiC void-less electronic package An electronic package designed to package silicon carbide discrete components for silicon carbide chips. The electronic package allows thousands of power cycles and/or temperature cycles between −55° C. to 300° C. The present invention can also tolerate continuo... | 10/14/2008 |
| 7402458 | Stress relieved flat frame for DMD window An improved window frame and window piece for a micromirror assembly is disclosed herein. The window frame includes a stress-relieving contour positioned in the middle of the frame that can absorb the mechanical stresses applied to the window frame from the ceramic ... | 07/22/2008 |
| 7371618 | Method of manufacturing wafer-level chip-size package and molding apparatus used in the method Provided are a method of manufacturing wafer-level chip-size packages and a molding apparatus suitable for practicing the method whereby a semiconductor wafer having a plurality of semiconductor chips formed thereon may be encapsulated. The semiconductor wafer, typi... | 05/13/2008 |
| 7368391 | Methods for designing carrier substrates with raised terminals A method for designing a carrier substrate includes configuring at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. The me... | 05/06/2008 |
| 7352070 | Polymer encapsulated electrical devices Improved encapsulated, overmolded and/or underfilled electrical components having a complete encapsulation, overmolding and/or underfilling with a coefficient of thermal expansion that is uniform and substantially free of gradients includes a polymeric matrix and an... | 04/01/2008 |
| 7332806 | Thin, thermally enhanced molded package with leadframe having protruding region A semiconductor die package. It includes (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate ... | 02/19/2008 |
| 7329620 | System and method for providing an integrated circuit having increased radiation hardness and reliability A system and method is disclosed for providing an integrated circuit that has increased radiation hardness and reliability. A device active area of an integrated circuit is provided and a layer of radiation resistant material is applied to the device active area of ... | 02/12/2008 |
| 7327032 | Semiconductor package accomplishing fan-out structure through wire bonding Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can ... | 02/05/2008 |
| 7323769 | High performance chip scale leadframe package with thermal dissipating structure and annular element and method of manufacturing package An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face.... | 01/29/2008 |
| 7319042 | Method and apparatus for manufacture and inspection of semiconductor device A semiconductor device is manufactured in such a way that a semiconductor chip connected with leads whose internal ends are interconnected with bonding wires are completely sealed and enclosed in a resin corresponding to a package while external ends of leads are ex... | 01/15/2008 |
| 7300824 | Method of packaging and interconnection of integrated circuits A method is disclosed for packaging semiconductor chips on a flexible substrate employing thin film transfer. The semiconductor chips are placed on a temporary adhesive substrate, then covered by a permanent flexible substrate with a casting layer for planarizingly ... | 11/27/2007 |
| 7298046 | Semiconductor package having non-ceramic based window frame A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled ... | 11/20/2007 |
| 7276398 | System and method for hermetically sealing a package A method for hermetically sealing a package includes applying a light or energy active resist to a fill port to act as a temporary hermetic seal, patterning the resist, and applying a solder to the fill port, wherein the solder is configured to serve as a hermetic s... | 10/02/2007 |
| 7247951 | Chip carrier with oxidation protection layer A chip carrier comprising a laminated layer and an oxidation protection layer is provided. The oxidation protection layer is a non-electrolytic metallic coating or an organic oxidation protection film on the surface of bonding finger pads or other contacts formed by... | 07/24/2007 |
| 7242085 | Semiconductor device including a semiconductor chip mounted on a metal base A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10A). A... | 07/10/2007 |
| 7233030 | Device transfer method and panel A device transfer method includes the steps of: covering a plurality of devices, which have been formed on a substrate, with a resin layer; forming electrodes in the resin layer in such a manner that the electrodes are connected to the devices; cutting the resin lay... | 06/19/2007 |
| 7230331 | Chip package structure and process for fabricating the same A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip... | 06/12/2007 |
| 7224053 | Semiconductor device responsive to different levels of input and output signals and signal processing system using the same A semiconductor device which integrates a plurality of semiconductor chips into a single package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a plurality of first bonding pads outputting first signals hav... | 05/29/2007 |
| 7196410 | Wafer packaging and singulation method A multi-device lid for a micro device wafer has a plurality of micro devices. The multi-device lid includes a multi-lid substrate configured to cover the plurality of micro devices of the micro device wafer. The multi-lid substrate has a trench pattern with intersec... | 03/27/2007 |
| 7190060 | Three-dimensional stacked semiconductor package device with bent and flat leads and method of making same A three-dimensional stacked semiconductor package device includes first and second semiconductor package devices and a conductive bond. The first device includes a first insulative housing, a first semiconductor chip and a first lead that is bent outside the first i... | 03/13/2007 |
| 7163838 | Method and apparatus for forming a DMD window frame with molded glass An improved method for fabricating a window frame/window piece assembly is disclosed in this application. A window frame having an opening in its inner portion is provided. According to one aspect, the window frame can be formed from a unitary piece of sheet metal. ... | 01/16/2007 |
| 7138707 | Semiconductor package including leads and conductive posts for providing increased functionality A semiconductor package comprising a semiconductor die which has opposed first and second surfaces and at least first and second bond pads disposed on the second surface thereof. In addition to the semiconductor die, the semiconductor package includes at least one l... | 11/21/2006 |
| 7135754 | Chip type solid electrolytic capacitor having a small size and a simple structure In a chip type solid electrolytic capacitor including a capacitor element and a packaging resin covering the capacitor element, the packaging resin has a mount surface and a side surface adjacent to the mount surface. A terminal is electrically connected to the capa... | 11/14/2006 |
| 7132733 | Semiconductor device A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sea... | 11/07/2006 |
| 7119449 | Enhancement of underfill physical properties by the addition of thermotropic cellulose An electrical component having improved impact resistance and improved tolerance for thermal cycling, without sacrificing high-temperature performance, and without requiring unconventional and expensive manufacturing techniques includes an electric device mounted on... | 10/10/2006 |
| 7115984 | Semiconductor devices including peripherally located bond pads, intermediates thereof, assemblies, and packages including the semiconductor devices, and support elements for the semiconductor devices A semiconductor device package is disclosed which is substantially die-sized with respect to each of the X, Y and Z axes. The package includes outer connectors that are located along at least one peripheral edge thereof and that extend substantially across the heigh... | 10/03/2006 |
| 7042089 | Group III nitride compound semiconductor device An object of the present invention is to provide a large-size light-emitting device from which uniform light emission can be obtained. That is, in the present invention, in a device having an outermost diameter of not smaller than 700 μm, a distance from an ... | 05/09/2006 |
| 6984877 | Bumped chip carrier package using lead frame and method for manufacturing the same A semiconductor package such as a bumped chip carrier (BCC) package has projections extending from a lower surface of a resin encapsulant. Each projection has a concave depression formed thereon. By reflowing a solder layer, external terminals are formed to cover th... | 01/10/2006 |
| 6703691 | Quad flat non-leaded semiconductor package and method of fabricating the same A QFN (Quad Flat Non-leaded) semiconductor packaging technology is proposed, which can be used to package a semiconductor chip of a central-pad type having at least one row of bond pads arranged along a center line on one surface of the semiconductor chip... | 03/09/2004 |
| 6703696 | Semiconductor package A semiconductor package is comprised of a semiconductor device 4 mounted on a die-pad 3, a wire 6 for electrically connecting some electrodes of the semiconductor device 4 and terminals 5 of lead frame, wires 8 for bonding the other electrodes of semicond... | 03/09/2004 |
| 6700186 | Lead frame for a semiconductor device, a semiconductor device made from the lead frame, and a method of making a semiconductor device A lead frame for a semiconductor device. The semiconductor device has a sheet with oppositely facing sides and a thickness between the oppositely facing sides. The sheet has first and second unit lead frames. Each unit lead frame has a support for a semic... | 03/02/2004 |
| 6700192 | Leadframe and method of manufacturing a semiconductor device using the same A leadframe used for a leadless package (a semiconductor device) such as a quad flat non-leaded package (QFN) includes a die-pad portion disposed in a center of an opening defined by a frame portion, and a plurality of lead portions extending from the fra... | 03/02/2004 |
| 6700190 | Integrated circuit device with exposed upper and lower die surfaces An integrated circuit (IC) device comprising: 1) an integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and sidewalls extending between the first surface and the second surface; and 2) an integrated circuit (IC... | 03/02/2004 |
| 6700188 | Low-pin-count chip package having concave die pad and/or connections pads A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip wherein the die pad and the connection pads have a concave profile. A package body is for... | 03/02/2004 |
| 6700193 | Semiconductor package with elevated tub The semiconductor device includes tub 5 that is smaller than semiconductor chip 8, and which supports semiconductor chip 8; molded section 12 that is formed by resin-molding around semiconductor chip 8; suspension leads 4, including supporting port... | 03/02/2004 |
| 6700206 | Stacked semiconductor package and method producing same A semiconductor device package and method of fabricating same. The package includes a lead frame having a die paddle and a plurality of lead fingers. The active surface of a first semiconductor die is adhered to the underside of the die paddle and is elec... | 03/02/2004 |
| 6700189 | Resin sealed semiconductor device A semiconductor device in which a lead frame having inner connecting portions and outer connecting portions, a semiconductor chip having electrodes on the surface thereof, and metal wires for electrically connecting electrodes on the semiconductor chip an... | 03/02/2004 |
| 6700198 | Resin for semiconductor wire In order to improve adhesion between a plated film which functions as an external connection terminal of a semiconductor device and a surface of a resin protuberance and to improve reliability, a carrier substrate includes a metal substrate which is shape... | 03/02/2004 |
| 6696747 | Semiconductor package having reduced thickness A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of th... | 02/24/2004 |
| 6696749 | Package structure having tapering support bars and leads A package structure having tapering support bars and leads. The package structure has at least a lead frame, a die, a plurality of conductive wires and an encapsulating plastic body. The lead frame has a first surface and has at least a package unit. The ... | 02/24/2004 |
