Did You Know...
...that Robert Adler has the dubious distinction of being the Father of the Couch Potato? Back in 1955 Adler was employed by what was then Zenith Radio Corp., where he was charged to invent something that would allow viewers to turn down the TV volume without leaving their chairs. After a series of flops (such as a wired contraption that people tripped over), Adler hit on the idea of using sound waves. Thus the Remote Control was born...
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| Number | Title | Issue Date |
| 7443041 | Packaging of a microchip device A method of packaging a microchip device, an interposer for packaging, and a packaged microchip device. An interposer is placed on microchip devices. The interposer includes an aperture which extends from the interposer surface where external electrical contacts are... | 10/28/2008 |
| 7436062 | Semiconductor chip element, semiconductor chip element mounting structure, semiconductor chip element mounting device and mounting method An apparatus and method for improving the underfill filling of a semiconductor chip element 100 which is ultrasonically bonded to and mounted on a circuit board. A semiconductor chip element 100 includes a silicon chip 101 and a group of stud bu... | 10/14/2008 |
| 7417314 | Semiconductor chip assembly with laterally aligned bumped terminal and filler A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a bumped terminal and a filler, a connection joint that electrically connects the routing line and the pad, and an encapsulan... | 08/26/2008 |
| 7414319 | Semiconductor chip assembly with metal containment wall and solder terminal A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a metal containment wall and a solder terminal, and a connection joint that electrically connects the routing line and the pa... | 08/19/2008 |
| 7407877 | Self-coplanarity bumping shape for flip-chip A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the... | 08/05/2008 |
| 7405477 | Ball grid array package-to-board interconnect co-design apparatus A package-board co-design methodology preserves the signal integrity of high-speed signals passing from semiconductor packages to application PCBs. An optimal architecture of interconnects between package and PCB enhances the signal propagation, minimizes parasitic ... | 07/29/2008 |
| 7405474 | Low cost thermally enhanced semiconductor package In one embodiment, a device is packaged using a low-cost thermally enhanced ball grid array (LCTE-BGA) package. The device may include a die with its backside mounted to the bottom side of a multi-layer packaging substrate. Thermal vias may be formed through the sub... | 07/29/2008 |
| 7405478 | Substrate package structure and packaging method thereof A substrate package structure includes bumps disposed on a surface side of a first substrate and a surface side of a second substrate. The bump at the first substrate and the bump at the second substrate are press-fitted to each other while the one surface of the fi... | 07/29/2008 |
| 7400035 | Semiconductor device having multilayer printed wiring board A semiconductor device includes a support body, a first substrate provided on a surface at one side of the support body, a second substrate provided on a surface at the other side of the support body, and a semiconductor chip provided on the first substrate exposed ... | 07/15/2008 |
| 7400032 | Module assembly for stacked BGA packages Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays are disclosed. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrange... | 07/15/2008 |
| 7396752 | Method and apparatus for reducing cold joint defects in flip chip products An electronic device is disclosed with solder bumps treated to improve coplanarity and reduce the effects of poor solder bump surface quality, and a method of constructing same. An electronic device is placed against a flat plate and a controlled amount of force is ... | 07/08/2008 |
| 7394164 | Semiconductor device having bumps in a same row for staggered probing A semiconductor device has a plurality of bumps in a same row for staggered probing. The bumps in a same row are disposed on a chip and include a plurality of regular bumps and a plurality of irregular bumps. The regular bumps and the irregular bumps are intersperse... | 07/01/2008 |
| 7391112 | Capping copper bumps A structure including a substrate, a copper bump formed over the substrate, and a barrier layer comprising an alloy of at least one of iron and nickel, formed over the copper bump, and methods to make such a structure. ... | 06/24/2008 |
| 7375429 | Integrated circuit component and mounting method thereof Disclosed are an integrated circuit component capable of simply mounting at low cost a chip part which adjusts impedance of wiring patterns as well as capable of effectively reducing switching noise from an integrated circuit, and a method for mounting the chip part... | 05/20/2008 |
| 7372169 | Arrangement of conductive pads on grid array package and on circuit board The present invention discloses a dense arrangement in the conductors of a package and the corresponding conductive pads of a circuit board. The conductors and the corresponding conductive pads are separated into at least a first group in a peripheral region of the ... | 05/13/2008 |
| 7372151 | Ball grid array package and process for manufacturing same A process for manufacturing an integrated circuit package includes forming a plurality of solder balls on a first surface of a substrate and mounting a semiconductor die to the substrate such that bumps of the semiconductor die are electrically connected to conducti... | 05/13/2008 |
| 7372139 | Semiconductor chip package A semiconductor chip package may include a substrate, which may have bonding pads formed thereon. A semiconductor chip mounted on the substrate may have chip pads, and electrical connections for connecting the chip pads of the semiconductor chip to the substrate bon... | 05/13/2008 |
| 7368819 | Multilayer printed wiring board and multilayer printed circuit board In a multilayer printed wiring board having a plurality of laminated resin layers, a plurality of wiring patterns formed on the interfacial surface of the resin layers, and a plurality of lands formed on the outermost layer of the resin layers and on which the solde... | 05/06/2008 |
| 7368821 | BGA semiconductor chip package and mounting structure thereof In example embodiments of the present invention, a structure of a BGA semiconductor chip package includes a substrate having first and second surfaces, a semiconductor chip having a plurality of bonding pads, and mounted on the first surface of the substrate, and pl... | 05/06/2008 |
| 7361997 | Device package, a printed wiring board, and an electronic apparatus with efficiently spaced bottom electrodes including intervals between bottom electrodes of different lengths A device package, such as a BGA, to be mounted on a printed wiring board (PWB) is disclosed. The bottom electrodes of the device package are arranged in an array such that intervals between the edges of the bottom electrodes become different from place to place. The... | 04/22/2008 |
| 7355272 | Semiconductor device with stacked semiconductor chips of the same type A semiconductor device includes a wiring board, a first semiconductor chip (e.g. DRAM) that is flip-chip connected on the wiring board, a second semiconductor chip (e.g. DRAM) that is of the same type as the first semiconductor chip and is mounted face up on the fir... | 04/08/2008 |
| 7352061 | Flexible core for enhancement of package interconnect reliability An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In... | 04/01/2008 |
| 7352054 | Semiconductor device having conducting portion of upper and lower conductive layers A semiconductor device includes a base plate, at least one first conductive layer carried by the base plate, and a semiconductor constructing body formed on or above the base plate, and having a semiconductor substrate and a plurality of external connecting electrod... | 04/01/2008 |
| 7348269 | Manufacturing method of semiconductor device, semiconductor device, circuit board, electro-optic device, and electronic apparatus A method for manufacturing a semiconductor device with a bump electrode wherein the bump electrode includes a resin material as a core and at least a top surface covered with a conductive film. The method includes placing the resin material on a substrate on which a... | 03/25/2008 |
| 7341934 | Method for fabricating conductive bump of circuit board A method for fabricating conductive bumps of a circuit board is proposed. First of all, a circuit board having a first surface and a corresponding second surface is provided. A circuit structure having a plurality of conductive pads is formed on each of the first su... | 03/11/2008 |
| 7335975 | Integrated circuit stacking system and method The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs o... | 02/26/2008 |
| 7332801 | Electronic device An electronic device includes a first die that includes wires for bonding, a second die that includes an array of balls for bonding, and a substrate. The substrate includes bond sites for wires from the first die, and bond sites for the array of balls from the secon... | 02/19/2008 |
| 7327032 | Semiconductor package accomplishing fan-out structure through wire bonding Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can ... | 02/05/2008 |
| 7323780 | Electrical interconnection structure formation An electrical interconnection structure and method for forming. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer co... | 01/29/2008 |
| 7323778 | Semiconductor device with improved design freedom of external terminal A semiconductor device comprises: a semiconductor chip; an extension portion formed in contact with the side surfaces so as to surround the semiconductor chip; an insulating film formed on a surface of the extension portion and the semiconductor chip; each of a plur... | 01/29/2008 |
| 7319269 | Semiconductor device power interconnect striping A method and an apparatus for improving the delivery and filtering of power to a semiconductor device is disclosed by organizing out interconnects (pins, balls, pads or other interconnects) used to carry power in a striped configuration that shortens the conductive ... | 01/15/2008 |
| 7317254 | Semiconductor device mounting structure for reducing thermal stress and warpage A semiconductor device is composed of a circuit board, a semiconductor chip connected with the circuit board by a plurality of bumps. The semiconductor chip includes a center portion and a peripheral portion surrounding the center portion. The peripheral portion has... | 01/08/2008 |
| 7309924 | UBM for fine pitch solder ball and flip-chip packaging method using the same A flip-chip package for implementing a fine solder ball, and a flip-chip packaging method using the same. The flip-chip package includes a first wafer having a first electrode and a first under bump metal (UBM) formed on the first electrode and electrically connecte... | 12/18/2007 |
| 7307354 | Integrated circuit (IC) carrier assembly incorporating an integrated circuit (IC) retainer An integrated circuit (IC) carrier assembly includes a printed circuit board (PCB). A carrier is soldered to the PCB. The carrier includes a grid of electrical contact islands surrounding a receiving zone for receiving an IC. Pairs of adjacent islands are interconne... | 12/11/2007 |
| 7301232 | Integrated circuit package with carbon nanotube array heat conductor An integrated circuit package includes a die mounted on a substrate, an integrated heat spreader set above the die, and an array of carbon nanotubes mounted between the die and the integrated heat spreader. The integrated heat spreader is fixed on the substrate, and... | 11/27/2007 |
| 7298036 | Scaling of functional assignments in packages A family of package substrates adapted to receive a family of integrated circuits having different sizes and provide electrical connections between the integrated circuits and a circuit board. Each package substrate in the family includes a package substrate having ... | 11/20/2007 |
| 7298042 | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument A semiconductor device includes a semiconductor substrate in which an integrated circuit is formed and which includes interconnects and electrodes, the interconnects electrically connected with the semiconductor substrate, and the electrodes being formed on the inte... | 11/20/2007 |
| 7294928 | Components, methods and assemblies for stacked packages A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly e... | 11/13/2007 |
| 7294904 | Integrated circuit package with improved return loss A packaged integrated circuit includes an integrated circuit and a package substrate. A trace in the package substrate includes a first portion and a second, high-inductance, portion. The high-inductance portion of the trace is proximate to a port of the integrated ... | 11/13/2007 |
| 7291926 | Multi-chip package structure The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the su... | 11/06/2007 |
