"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
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| Number | Title | Issue Date |
| 7411297 | Microfeature devices and methods for manufacturing microfeature devices Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting... | 08/12/2008 |
| 7393719 | Increased stand-off height integrated circuit assemblies, systems, and methods Disclosed are integrated circuit assemblies with increased stand-off height and methods and systems for their manufacture. Methods of the invention provide for assembling a semiconductor device by aligning a die with a substrate and interposing solder between corres... | 07/01/2008 |
| 7387910 | Method of bonding solder pads of flip-chip package Disclosed herein is a method of bonding solder pads of a flip-chip package. This invention relates to a method of bonding solder pads having different sizes to each other, when a bonding operation is executed between a chip and a PCB, between chips, or between PCBs.... | 06/17/2008 |
| 7375429 | Integrated circuit component and mounting method thereof Disclosed are an integrated circuit component capable of simply mounting at low cost a chip part which adjusts impedance of wiring patterns as well as capable of effectively reducing switching noise from an integrated circuit, and a method for mounting the chip part... | 05/20/2008 |
| 7371676 | Method for fabricating semiconductor components with through wire interconnects A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a c... | 05/13/2008 |
| 7368758 | Method for hermetically housing optical components, and optical components produced according to said method A method is provided for producing a housing body for optoelectronic components that are reliable and inexpensive. The method creates a hermetic joint between a metal sleeve and a glass pane by joining together a housing element and a preferably metallic housing arr... | 05/06/2008 |
| 7368324 | Method of manufacturing self-supporting contacting structures A self-supporting contacting structure is directly produced on a component that does not have a housing by applying a layer made of non conducting material and a layer made of an electrically conductive material to the component and to a support and by subsequently ... | 05/06/2008 |
| 7368810 | Invertible microfeature device packages Invertible microfeature device packages and associated methods for manufacture and use are disclosed. A package in accordance with one embodiment includes a microfeature device having a plurality of device contacts, and a conductive structure electrically connected ... | 05/06/2008 |
| 7364943 | Method of bonding a microelectronic die to a substrate and arrangement to carry out method A method and an arrangement to bond a die to a substrate of a die-substrate combination to form a microelectronic package. The method comprises: providing the die-substrate combination including a die, a substrate, pre-connection bumps and an underfill material, the... | 04/29/2008 |
| 7358618 | Semiconductor device and manufacturing method thereof A semiconductor device having a semiconductor substrate, at least one of a protruding electrode and wiring formed on one surface of the semiconductor substrate, and a first resin film formed on this surface. The first resin film has elasticity low enough to reduce s... | 04/15/2008 |
| 7355280 | Method for forming a bump, semiconductor device and method of fabricating same, semiconductor chip, circuit board, and electronic instrument A method for forming a bump includes the steps of forming a resist layer so that a through-hole formed therein is located on a pad; and forming a metal layer to be electrically connected to the pad conforming to the shape of the through-hole. The metal layer is form... | 04/08/2008 |
| 7332821 | Compressible films surrounding solder connectors Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to t... | 02/19/2008 |
| 7332806 | Thin, thermally enhanced molded package with leadframe having protruding region A semiconductor die package. It includes (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate ... | 02/19/2008 |
| 7327031 | Semiconductor device and method of manufacturing the same There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening above Cu pad areas, is formed, and a barrier metal film is formed in t... | 02/05/2008 |
| 7314817 | Microelectronic device interconnects A microelectronic assembly including a plurality of conductive columns extending from a bond pad of a microelectronic device and a conductive adhesive on a land pad of a carrier substrate electrically attached to the conductive columns. ... | 01/01/2008 |
| 7309647 | Method of mounting an electroless nickel immersion gold flip chip package A flip chip package, apparatus and technique in which a ball grid array composed of a doped eutectic Pb/Sn solder composition is used. The dopant in the Pb/Sn solder forms a compound or complex with the phosphorous residue from the electroless nickel plating process... | 12/18/2007 |
| 7298049 | Submount for mounting semiconductor device A submount that enables the reliable mounting of a semiconductor light-emitting device on it, and a semiconductor unit incorporating the submount. A submount 3 comprises (a) a substrate 4; and (b) a solder layer 8 formed on the top surface 4 | 11/20/2007 |
| 7298047 | Electronic circuit device An electronic circuit device includes at least a first substrate and a second substrate, a spacer substrate interposed between the first substrate and the second substrate, an electronic component interposed between the first substrate and the second substrate, and ... | 11/20/2007 |
| 7273806 | Forming of high aspect ratio conductive structure using injection molded solder Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention ... | 09/25/2007 |
| 7268438 | Semiconductor element including a wet prevention film A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of suc... | 09/11/2007 |
| 7247514 | Semiconductor device and method for producing the same A method for producing a semiconductor device of the present invention includes forming a surface electrode on a semiconductor element, forming a solder layer by plating on one principal surface of the surface electrode, mounting the semiconductor element on the sub... | 07/24/2007 |
| 7245011 | Prevention of contamination on bonding pads of wafer during SMT A semiconductor device is disclosed for preventing contamination on its bonding pads during mounting an electronic component, such as surface mount device (SMD). The semiconductor device includes a semiconductor substrate, a plurality of jointing material and at lea... | 07/17/2007 |
| 7245024 | Electronic assembly with reduced leakage current An electronic assembly includes a substrate and at least one surface mounted electronic component. The substrate includes a first side and a second side opposite the first side. The first side of the substrate includes a plurality of conductive traces formed thereon... | 07/17/2007 |
| 7235871 | Stacked microelectronic dies An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, the method includes positioning a first packaged microelectronic device adjacent to a support member having support member circuitry, with the fi... | 06/26/2007 |
| 7233072 | Electronic part and surface treatment method of the same There is provided a surface treatment method for an electronic part, which uses a metal not containing lead and tin and having excellent solder wettability, is economical and has high reliability. In the surface treatment method for the electronic part in which a so... | 06/19/2007 |
| 7230320 | Electronic circuit device with reduced breaking and cracking In an electronic circuit device including a substrate including a front surface on which an electronic circuit element is mounted and a reverse surface opposite to the front surface in a thickness direction of the substrate, an electrically conductive terminal membe... | 06/12/2007 |
| 7227268 | Placement of sacrificial solder balls underneath the PBGA substrate The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the pac... | 06/05/2007 |
| 7221045 | Flat chip semiconductor device and manufacturing method thereof A flip chip semiconductor device having an improved structure and a method of manufacturing the flip chip semiconductor device, in which a semiconductor chip can be more securely joined to a lead frame while preventing contact defects between the two. The flip chip ... | 05/22/2007 |
| 7215030 | Lead-free semiconductor package A package substrate includes die solder pads and pin solder fillets. The pin solder fillets might comprise between approximately 90 wt % to approximately 99 wt % tin and approximately 10 wt % to 1 wt % antimony. The die solder pads might comprise between approximate... | 05/08/2007 |
| 7211902 | Method of forming a bonding pad structure A semiconductor device having a semiconductor substrate and a bonding pad portion formed on the semiconductor substrate, the bonding pad portion having: an insulating film formed on the semiconductor substrate and a first-level conductive pad layer of a large island... | 05/01/2007 |
| 7208347 | Connection technology for power semiconductors comprising a layer of electrically insulating material that follows the surface contours A layer of electrically insulating material is applied to a substrate and a component located thereon, in such a way that said layer follows the surface contours. ... | 04/24/2007 |
| 7205661 | Projected contact structures for engaging bumped semiconductor devices and methods of making the same A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom for contacting at least one solder ball of a bumped integrated circuit (IC) device, such as a bumped die ... | 04/17/2007 |
| 7205660 | Wafer level chip scale package having a gap and method for manufacturing the same A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a s... | 04/17/2007 |
| 7183652 | Electronic component and electronic configuration An electronic component includes a substrate with outer contact areas comprising copper. Lead-free solder bumps are disposed on the outer contact areas of the electronic component. An electronic configuration includes an electronic component and a printed circuit bo... | 02/27/2007 |
| 7166925 | Semiconductor devices having stereolithographically fabricated protective layers thereon through which contact pads are exposed and assemblies including the same A method for forming packaged substrates includes using a stereolithographic process to form a protective dielectric polymeric sealing structure on at least the active surface of the substrate which includes one or more flip-chip dice. In addition, the invention enc... | 01/23/2007 |
| 7164148 | Light emitting device A CAN package light emitting device comprises a semiconductor laser 1 bonded on a sub mount 6 and a CAN package 2 for housing the semiconductor laser 1 bonded on the sub mount 6. The CAN package 2 comprises a fixing structur... | 01/16/2007 |
| 7164208 | Semiconductor device and method for manufacturing the same There is provided a semiconductor device in which the junction strength of land portions and external terminals is increased, the disconnection of the external terminal is surely prevented, and the connection reliability is ensured over an extended period of time. A... | 01/16/2007 |
| 7160796 | Method for manufacturing wiring board and semiconductor device Pads to be used for flip chip bonding and wire bonding are pattern-formed on a surface of a substrate. The pads to be used for flip chip bonding are shielded. Plating is applied to each of the pads to be used for wire bonding. Bonding pads for wire bonding is shield... | 01/09/2007 |
| 7135771 | Self alignment features for an electronic assembly Some embodiments of the present invention relate to an electronic assembly that includes a substrate and a die. The electronic assembly further includes an alignment bump on one of the die and the substrate and a group of mating bumps on the other of the die and the... | 11/14/2006 |
| 7122894 | Wiring substrate and process for manufacturing the same A wiring substrate incorporating nickel-plated copper terminal pads for solder bumps, wherein a nickel plating layer constituting the nickel plated copper terminal pads has a phosphorus content of 8.5 to 15.0% by mass and is covered with a gold plating layer. ... | 10/17/2006 |