Did You Know...
...that Thomas Edison's patent application on his phonograph was approved by the Patent Office in just seven weeks? In contrast, it took Gordon Gould, the inventor of the laser, 30 years to obtain his patent -- finally awarded in 1988!
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| Number | Title | Issue Date |
| 7414309 | Encapsulated electronic part packaging structure An encapsulated electronic part packaging structure includes a step of mounting an electronic part having a connection terminal and a passivating film to cover the connection terminal, mounted on a body to direct the connection terminal upward. An insulating layer i... | 08/19/2008 |
| 7397103 | Semiconductor with damage detection circuitry Disclosed herein are novel damage detection circuitries implemented on the periphery of a semiconductor device. The circuitries disclosed herein enable the easy identification of cracks and deformation, and other types of damage that commonly occur during test and a... | 07/08/2008 |
| 7375421 | High density multilayer circuit module Thinning and stacking are essential for circuit modules used for mobile devices of various kinds, smart cards, memory cards and the like. These demands make the manufacture of the circuit modules more complicated or less reliable due to delamination. A circuit modul... | 05/20/2008 |
| 7351656 | Semiconductor device having oxidized metal film and manufacture method of the same A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in ... | 04/01/2008 |
| 7335964 | Semiconductor structures In one aspect, the invention encompasses a semiconductor processing method of forming a material over an uneven surface topology. A substrate having an uneven surface topology is provided. The uneven surface topology comprises a valley between a pair of outwardly pr... | 02/26/2008 |
| 7332799 | Packaged chip having features for improved signal transmission on the package A packaged chip is provided which includes a package element on which a signal-bearing conductive trace has an edge laterally adjacent to an edge of a reference conductive trace (e.g., ground trace) on the same face of a dielectric element, the two traces together f... | 02/19/2008 |
| 7327031 | Semiconductor device and method of manufacturing the same There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening above Cu pad areas, is formed, and a barrier metal film is formed in t... | 02/05/2008 |
| 7291875 | Semiconductor device with double barrier film A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hol... | 11/06/2007 |
| 7285842 | Siloxane epoxy polymers as metal diffusion barriers to reduce electromigration Structures employing siloxane epoxy polymers as diffusion barriers adjacent conductive metal layers are disclosed. The siloxane epoxy polymers exhibit excellent adhesion to conductive metals, such as copper, and provide an increase in the electromigration lifetime o... | 10/23/2007 |
| 7285858 | Semiconductor device and its manufacture method capable of preventing short circuit of electrodes when semiconductor device is mounted on sub-mount substrate A confronting surface of a substrate faces a first surface of a semiconductor element. Extension layers are formed on the substrate at positions facing electrodes on the semiconductor element. A levee film is disposed on one of the confronting surface and the first ... | 10/23/2007 |
| 7265437 | Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achiev... | 09/04/2007 |
| 7247947 | Semiconductor device comprising a plurality of semiconductor constructs A semiconductor device includes a first semiconductor construct provided on a base plate and having a semiconductor substrate and external connection electrodes. An insulating layer is provided on the base plate around the first semiconductor construct. An upper lay... | 07/24/2007 |
| 7215027 | Electrical coupling stack and processes for making same A process of making an electrical coupling stack is disclosed. A conductive structure is coupled to a substrate. The coupling includes a crystalline salicide first structure above the conductive structure, a nitrogen-containing amorphous salicide second structure ab... | 05/08/2007 |
| 7193314 | Semiconductor devices and substrates used in thereof A substrate used in a semiconductor device. The substrate includes a first wiring layer, a second wiring layer, and an interconnection-wiring layer. The first wiring layer includes a plurality of first pads, and the second wiring layer includes a plurality of second... | 03/20/2007 |
| 7193324 | Circuit structure of package substrate A circuit structure for a package substrate or a circuit board is provided. The circuit structure has a dielectric layer with an upper surface and a lower surface, at least a first line and at least a second line. The first line is disposed on the dielectric layer o... | 03/20/2007 |
| 7180168 | Stacked semiconductor chips A groove is formed on a semiconductor substrate having integrated circuits and electrodes from a first surface. An insulating layer is formed on an inner surface of the groove. A conductive layer is formed on the insulating layer above the inner surface of the groov... | 02/20/2007 |
| 7173330 | Multiple chip semiconductor package A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated wit... | 02/06/2007 |
| 7078812 | Routing differential signal lines in a substrate A method for routing signals in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with at least one differential signal line pair aligned along a common plane that is substantially transverse to a top surfa... | 07/18/2006 |
| 6870220 | Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses A gate structure for a semiconductor device includes a shielding electrode and a switching electrode. Respective portions of the shielding electrode are disposed above said drain region and said well region. A first dielectric layer is disposed between the shielding... | 03/22/2005 |
| 6700205 | Semiconductor devices having contact plugs and local interconnects Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are comp... | 03/02/2004 |
| 6696368 | Titanium boronitride layer for high aspect ratio semiconductor devices Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The contacts are useful for providing electrical connection to active components beneath an insulation layer in integrated circuits such as m... | 02/24/2004 |
| 6696761 | Method to encapsulate copper plug for interconnect metallization An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is part... | 02/24/2004 |
| 6693360 | Static type semiconductor memory device A memory cell of a static type semiconductor memory device includes a gate electrode of an MOS transistor formed on a main surface of semiconductor substrate via an insulator film, an interlayer insulator film covering the gate electrode, a set of contact... | 02/17/2004 |
| 6693032 | Method of forming a contact structure having an anchoring portion A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive la... | 02/17/2004 |
| 6690093 | Metal contact structure in semiconductor device and method for forming the same A metal contact structure of a semiconductor device and a method for forming the same, wherein an upper conductive layer is formed by etching a metal layer, which fills a contact hole and is formed on the entire surface of an interlayer dielectric film an... | 02/10/2004 |
| 6688584 | Compound structure for reduced contact resistance Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first r... | 02/10/2004 |
| 6683351 | Semiconductor device having structures that can avoid deterioration caused by the manufacturing processing A semiconductor device restricting the antenna effect without complicating the manufacturing process and a manufacturing method of such a semiconductor device are provided. In addition, a semiconductor device ensuring matching or equality in characteristi... | 01/27/2004 |
| 6680538 | Semiconductor device for suppressing detachment of conductive layer A semiconductor device and a method for manufacturing the semiconductor device are provided in which a lower plug electrically connected with an active region of a wafer has a recession, and a conductive layer has a projection fitted into the recession of... | 01/20/2004 |
| 6674171 | Semiconductor device with a low resistance wiring An impurity region is formed on the surface of a semiconductor substrate. An insulating layer is provided on the semiconductor substrate to cover the impurity region. A trench for defining a wiring layer is provided on the surface of the insulating layer.... | 01/06/2004 |
| 6670711 | Semiconductor device including low dielectric constant insulating film formed on upper and side surfaces of the gate electrode A semiconductor device having a self-aligned contact structure. To determine the position of a contact plug in a self-aligned manner, silicon nitride films are provided around a gate electrode and a bitline, respectively. Between the gate electrode and bi... | 12/30/2003 |
| 6664159 | Mixed metal nitride and boride barrier layers Mixed metal aluminum nitride and boride diffusion barriers and electrodes for integrated circuits, particularly for DRAM cell capacitors. Also provided are methods for CVD deposition of Mx Aly Nz Bw alloy diffus... | 12/16/2003 |
| 6664585 | Semiconductor memory device having multilayered storage node contact plug and method for fabricating the same A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The semiconductor memory device includes a multi-layered stora... | 12/16/2003 |
| 6660456 | Technique for the size reduction of vias and other images in semiconductor chips A method of forming openings on a semiconductor wafer comprising an initial step of providing a first film layer over the semiconductor wafer. A first opening in the first film layer is created by transferring an image of the first opening from a photores... | 12/09/2003 |
| 6656833 | Method of DRAM A semiconductor device is fabricated by forming a first insulating layer, in which an etch stopper and a first contact plug are formed so that the etch stopper surrounds an end portion of the first contact plug and the latter extends through the first ins... | 12/02/2003 |
| 6657280 | Redundant interconnect high current bipolar device A bipolar transistor having a base contact surrounded by an emitter contact. A plurality of wires extending from the base contact and the emitter contact of the bipolar transistor, wherein the wires of the base contact are stacked higher than the wires of... | 12/02/2003 |
| 6653690 | Semiconductor device comprising high density integrated circuit having a large number of insulated gate field effect transistors It is a purpose of the invention to provide a semiconductor device comprising a high density integrated circuit having a large number of insulated gate field effect transistors having minute size and improved performance and uniformity. The source contact... | 11/25/2003 |
| 6653739 | Semiconductor device A contact plug 26 formed between adjacent two wirings 14 according to a self-aligning manner is provided. An interlayer oxide film 12 is provided on a substrate layer 10 conductive to the bottom face of the contact plug. A lower insulating film 32 formed ... | 11/25/2003 |
| 6653222 | Plasma enhanced liner A method and structure for forming a refractory metal liner, includes depositing a layer of refractory metal on a first conductive layer, at least half of the depositing being carried out in the presence of an amount of passivating agent that is sufficien... | 11/25/2003 |
| 6650017 | Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate a... | 11/18/2003 |
| 6645849 | Method for manufacturing semiconductor device for suppressing detachment of conductive layer A semiconductor device and a method for manufacturing the semiconductor device are provided in which a lower plug electrically connected with an active region of a wafer has a recession, and a conductive layer has a projection fitted into the recession of... | 11/11/2003 |
