Class 257/E23.002 - Details not otherwise provided for, e.g., protection against moisture (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E23.001.
No. of patents: 183
Last issue date: 10/14/2008

«First «Previous1 2 3 4 5 Next»Last»

Number	Title	Issue Date
7436047	Wafer having scribe lanes suitable for sawing process, reticle used in manufacturing the same, and method of manufacturing the same A wafer that is less susceptible to chipping or peeling during a sawing process is disclosed. The wafer includes a plurality of chips, scribe lanes formed between the plurality of chips, and a passivation film, which is formed on the plurality of chips and the scrib...	10/14/2008
7435993	High temperature, high voltage SiC void-less electronic package An electronic package designed to package silicon carbide discrete components for silicon carbide chips. The electronic package allows thousands of power cycles and/or temperature cycles between −55° C. to 300° C. The present invention can also tolerate continuo...	10/14/2008
7427803	Electromagnetic shielding using through-silicon vias An isolation structure for electromagnetic interference includes a semiconductor substrate, a first integrated circuit in the semiconductor substrate, a second integrated circuit in the semiconductor substrate, and an isolation structure in a direct path between the...	09/23/2008
7411257	Semiconductor device having guard ring and manufacturing method thereof An interlayer insulation film is etched to form contact holes in an integrated circuit part. At this time, a trench is not formed in a guard ring part. Subsequently, ion implantation is carried out in source/drain regions in a peripheral circuit part for contact com...	08/12/2008
7408259	Sheet to form a protective film for chips A sheet to form a protective film for chips includes a release sheet and a protective film forming layer formed on a detachable surface of the release sheet. The protective film forming layer includes a thermosetting and/or energy ray-curable component and a binder ...	08/05/2008
7405459	Semiconductor device comprising porous film The present invention provides a zeolite sol which can be formed into a porous film that can be thinned to an intended thickness by a method used in the ordinary semiconductor process, that excels in dielectric properties, adhesion, film consistency and mechanical s...	07/29/2008
7405455	Semiconductor constructions and transistor gates One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewa...	07/29/2008
7393716	Encapsulated organic semiconductor device and method A semiconductor device comprising organic semiconductor material (14) has one or more barrier layers (16) disposed at least partially thereabout to protect the organic semiconductor material (14) from environment-driven changes that typically le...	07/01/2008
7390742	Method for producing a rewiring printed circuit board The invention relates to a method for producing a rewiring printed circuit board with a substrate wafer having passage connections between a first and a second surface. One embodiment of the method comprises applying and patterning masking layers on the first and th...	06/24/2008
7385277	Semiconductor chip and method of fabricating the same A semiconductor chip may include a semiconductor substrate that may have a semiconductor device pattern. A passivation layer may be provided on a surface of the semiconductor substrate. At least one elastic protecting layer may be provided on the passivation layer. ...	06/10/2008
7348594	Test structures and models for estimating the yield impact of dishing and/or voids A test structure comprising a test pattern is formed on a substrate. The test pattern includes a first comb structure having a plurality of tines, and a second structure. The second structure may be a snake structure having a plurality of side walls or a second comb...	03/25/2008
7307350	Integrated circuit chip bonding sheet and integrated circuit package An IC chip bonding sheet having adhesive resin layers formed on both faces of a porous polytetrafluoroethylene layer comprising a porous polytetrafluoroethylene sheet, the porous polytetrafluoroethylene layer retaining porous voids, and the adhesive resin layers com...	12/11/2007
7307337	Resin-molded semiconductor device having posts with bumps and method for fabricating the same A semiconductor apparatus includes a semiconductor device to be mounted on a circuit board; a plurality of conductive posts electrically connected to the semiconductor device; and a plurality of conductive bumps each provided on an outer end of each of the conductiv...	12/11/2007
7285862	Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where...	10/23/2007
7282776	Method and structure for coupling two microcircuits A system in a package (SIP) or multi-chip module (200, 300, 400) (MCM) uses an electron beam (235, 335, 435) for electrically coupling between microcircuits (230, 330, 430) and (232, 332, 432). In one embodiment, the micro-circuits (23...	10/16/2007
7233045	Semiconductor device and system Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therei...	06/19/2007
7224056	Back-face and edge interconnects for lidded package A packaged microelectronic device is provided which includes: (a) a unit having a chip with an upwardly-facing front surface and a downwardly-facing rear surface, a lid overlying at least a portion of the front surface of the chip, the lid having a top surface facin...	05/29/2007
7151050	Method for fabricating electrical connection structure of circuit board A method for fabricating an electrical connection structure of a circuit board is proposed. A patterned resist layer is formed on the circuit board having a plurality of conductive pads, and a plurality of openings is formed in the resist layer to expose the conduct...	12/19/2006
7112886	Packaging structure with a plurality of drill holes formed directly below an underfill layer A packaging structure for an optical sensor with drill holes formed directly below an underfill layer includes a substrate having a plurality of drill holes, a plurality of vias, a plurality of traces, a plurality of gold wires, an underfill layer, a die having a pl...	09/26/2006
7091605	Highly moisture-sensitive electronic device element and method for fabrication A highly moisture-sensitive element and method of making such element includes an encapsulation enclosure encapsulating all of the highly moisture-sensitive electronic devices on a substrate and a sealing material positioned between the substrate and the encapsulati...	08/15/2006
7091583	Method and structure for prevention leakage of substrate strip The present invention provides a structure and a method for prevention leakage of a substrate strip. The substrate strip includes an edge portion and a plurality of units. A patterned metal layer on a surface of the substrate strip includes at least one plating bus ...	08/15/2006
6703701	Semiconductor device with integrated circuit elements of group III-V comprising means for preventing pollution by hydrogen A semiconductor device comprising integrated circuit elements realized by means of a stack of layers of semiconductor materials provided on a substrate of semiconductor material and comprising means for preventing the pollution of the circuit elements and...	03/09/2004
6693336	Intergrated circuit chip package with reduced parameter offsets A semiconductor encapsulated package is provided with buffer chambers established through external openings aligned with stress sensitive circuitry sites, wherein the viscosity of the encapsulating molding compound and the opening are interrelated to limi...	02/17/2004
6683329	Semiconductor device with slot above guard ring A semiconductor device includes an electronic circuit, a metal guard ring surrounding the electronic circuit, and a passivation layer covering the electronic circuit and guard ring. The passivation layer has a slot extending from the surface of the device...	01/27/2004
6646346	Integrated circuit metallization using a titanium/aluminum alloy An integrated circuit metallization structure using a titanium/aluminum alloy, and a method to generate such a structure, provide reduced leakage current by allowing mobile impurities such as water, oxygen, and hydrogen to passivate structural defects in ...	11/11/2003
6635572	Method of substrate silicon removal for integrated circuit devices An integrated circuit die coupled to a package substrate and having circuitry in a circuit side opposite a back side is etched in a manner that inhibits the erosion of underfill material that is used around the periphery of the die and between the die and...	10/21/2003
6613586	HYDROGEN BARRIER ENCAPSULATION TECHNIQUES FOR THE CONTROL OF HYDROGEN INDUCED DEGRADATION OF FERROELECTRIC CAPACITORS IN CONJUNCTION WITH MULTILEVEL METAL PROCESSING FOR NON-VOLATILE INTEGRATED CIRCUIT MEMORY DEVICES A hydrogen barrier encapsulation technique for the control of hydrogen induced degradation of ferroelectric capacitors in non-volatile integrated circuit memory devices. The resultant device structure ameliorates the hydrogen induced degradation of ferroe...	09/02/2003
6608372	Surface mountable chip type semiconductor device and manufacturing method A surface mountable chip type semiconductor device comprises: first and second conductive land areas which are formed on an insulating substrate and which are electrically coupled with each other; a conductive post formed on the first conductive land area...	08/19/2003
6605865	Semiconductor package with optimized leadframe bonding strength A semiconductor package including a sealing part which is bonded to a lead frame. The lead frame is formed to include portions of reduced thickness for purposes of providing maximum crack prevention during a singulation process involved in the manufacture...	08/12/2003
6596561	Method of manufacturing a semiconductor device using reinforcing patterns for ensuring mechanical strength during manufacture The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, t...	07/22/2003
6563219	Passivation integrity improvements An exemplary implementation of the invention is a process for forming passivation protection on a semiconductor assembly by the steps of: forming a layer of oxide over patterned metal lines having sidewalls; forming a first passivation layer of silicon ni...	05/13/2003
6555924	Semiconductor package with flash preventing mechanism and fabrication method thereof A semiconductor package and a fabricating method thereof are proposed, in which a substrate is prepared for having at least one flash preventing mechanism disposed on a surface of the substrate corresponding to a position in front of an entry of an air ve...	04/29/2003
6551862	Semiconductor device and method of manufacturing the same A semiconductor device is disclosed, comprising a tape substrate which supports a semiconductor chip, an insulating adhesive layer disposed between the semiconductor chip and the tape substrate, an insulating sheet member laminated to the insulating adhes...	04/22/2003
6541373	Manufacture method for semiconductor with small variation in MOS threshold voltage After a MOS type transistor is formed on the surface of a semiconductor substrate, an interlayer insulating film covering the transistor is formed. The insulating film includes a silicon oxide film made of hydrogen silsesquioxane resin in a ceramic state....	04/01/2003
6531344	High frequency gallium arsenide MMIC die coating method A moisture resistant conformal coating (14) effectively protects high frequency circuits such as gallium arsenide MMICs from humidity and environmental contamination without the performance degradation inherent in conventionally applied conformal coatings...	03/11/2003
6531766	Semiconductor package and production method thereof For providing a semiconductor package with improved moisture resistance and high reliability and a production method thereof, a solder resist is also provided in an appropriate thickness between electrodes of conductor circuits on a surface of a substrate...	03/11/2003
6525398	Semiconductor device capable of preventing moisture-absorption of fuse area thereof A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening port...	02/25/2003
6518090	Semiconductor device and manufacturing method thereof A semiconductor device includes a circuit board on which a semiconductor chip is mounted via an adhesive resin layer and through which a moisture drain hole is formed. A pit part having a width wider than a diameter of the moisture drain hole is formed in...	02/11/2003
6515343	Metal-to-metal antifuse with non-conductive diffusion barrier An antifuse is disposed between a first and second conductor. An insulating diffusion barrier (for example, silicon nitride) covers the sidewalls of the antifuse to inhibit contaminants (for example, copper, chlorine, fluorine, sodium, potassium, and mois...	02/04/2003
6509650	Electronic device, and method of patterning a first layer The electronic device (1) has a layer (11) of a material comprising a first and a second element. This material has an amorphous and a crystalline state. A transition from the amorphous to the crystalline state can be effected by heating of the material t...	01/21/2003

«First «Previous1 2 3 4 5 Next»Last»

PatentStorm

Quotables

PatentStorm News

Class 257/E23.002 - Details not otherwise provided for, e.g., protection against moisture (EPO)