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| Number | Title | Issue Date |
| 7442576 | Placement of absorbing material in a semiconductor device A semiconductor device is provided that includes a hermetically sealed housing having a top member and a bottom member. A semiconductor die is enclosed within the housing and absorbing material is positioned under the semiconductor die. ... | 10/28/2008 |
| 7436047 | Wafer having scribe lanes suitable for sawing process, reticle used in manufacturing the same, and method of manufacturing the same A wafer that is less susceptible to chipping or peeling during a sawing process is disclosed. The wafer includes a plurality of chips, scribe lanes formed between the plurality of chips, and a passivation film, which is formed on the plurality of chips and the scrib... | 10/14/2008 |
| 7429797 | Electronic device and carrier substrate Consistent with an example embodiment, an electronic device comprises a semiconductor device, particularly an integrated circuit, and a carrier substrate with conductive layers on the first side and the second side, and voltage supply and ground connections mutually... | 09/30/2008 |
| 7425462 | Methods relating to the reconstruction of semiconductor wafers for wafer-level processing Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in ... | 09/16/2008 |
| 7420267 | Image sensor assembly and method for fabricating the same An assembly device of an image sensor chip is disclosed. A flexible circuit has a die-attached portion, a plurality of bendable portions, and a plurality of bonding portions where the bendable portions extend from the die-attached portion and are connected to the co... | 09/02/2008 |
| 7416910 | Pyramid socket suspension An apparatus and method for flexibly suspending a sensing mechanism between a pair of cover plates, including a sensing mechanism formed in a crystalline silicon substrate; a pair of cover plates formed in crystalline silicon substrates; a first plurality of complem... | 08/26/2008 |
| 7417324 | Semiconductor device and method for manufacturing the same A semiconductor device is composed of a semiconductor chip, aluminum pads formed on the semiconductor chip, alloy ball bumps, which are formed on the aluminum pads, containing gold and Pd, and gold wires, which are connected to the alloy ball bumps, having a surface... | 08/26/2008 |
| 7417309 | Circuit device and portable device with symmetrical arrangement To provide a circuit device freed from constrains of a mounting direction. The circuit device according to the present invention includes: a conductive pattern for forming a die pad, a first bonding pad, and a second bonding pad; and a semiconductor element (TR) att... | 08/26/2008 |
| 7411304 | Semiconductor interconnect having conductive spring contacts An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer ... | 08/12/2008 |
| 7408251 | Semiconductor packaging device comprising a semiconductor chip including a MOSFET A thin semiconductor device difficult to cause breakage of a semiconductor chip is disclosed. The semiconductor device comprises a sealing member, a semiconductor chip positioned within the sealing member, the semiconductor chip having a source electrode and a gate ... | 08/05/2008 |
| 7405474 | Low cost thermally enhanced semiconductor package In one embodiment, a device is packaged using a low-cost thermally enhanced ball grid array (LCTE-BGA) package. The device may include a die with its backside mounted to the bottom side of a multi-layer packaging substrate. Thermal vias may be formed through the sub... | 07/29/2008 |
| 7400046 | Semiconductor device with guard rings that are formed in each of the plural wiring layers A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first ins... | 07/15/2008 |
| 7387913 | 3D optoelectronic micro system A 3D micro optical switching system (3D-MOSS) is fabricated by dividing an optical switching system into several blocks, creating optoelectronic layers where optical switches or tunable filters in each block are disposed, laminating the optoelectronic layers by conn... | 06/17/2008 |
| 7378721 | Chip on lead frame for small package speed sensor A sensor package apparatus includes a lead frame substrate that supports one or more electrical components, which are connected to and located on the lead frame substrate. A plurality of wire bonds are also provided, which electrically connect the electrical compone... | 05/27/2008 |
| 7378727 | Memory device and a method of forming a memory device A memory device includes a semiconductor substrate having a surface, a plurality of first and second conductive lines, a plurality of memory cells, and a plurality of landing pads. Each of the first conductive lines has a line width wb and two neighboring ones of th... | 05/27/2008 |
| 7378748 | Solid-state imaging device and method for manufacturing the same A solid-state imaging device comprises a housing in which a base and ribs forming a rectangular frame are formed in one piece by a resin; a plurality of metal lead pieces embedded in the housing, each of which has an internal terminal portion facing an internal spac... | 05/27/2008 |
| 7372142 | Vertical conduction power electronic device package and corresponding assembling method A vertical conduction power electronic device package and corresponding assembly method comprising at least a metal frame suitable to house at least a plate or first semiconductor die having at least a first and a second conduction terminal on respective opposed sid... | 05/13/2008 |
| 7372135 | Multi-chip image sensor module A multi-chip image sensor module includes a flexible module board, an image sensor chip, a transparent cover, and at least an IC chip. The flexible module board has a first die-attached portion, a second die-attached portion, at least one bent portion, and at least ... | 05/13/2008 |
| 7368809 | Pillar grid array package A pillar grid array package (PGA) includes a substrate, a chip disposed on top of the substrate, and a plurality of stud bumps disposed on bottom of the substrate. The stud bumps are formed in an array and each has a flattened top to electrically connect to a printe... | 05/06/2008 |
| 7368749 | Method of detecting misalignment of ion implantation area A method of detecting misalignment of ion implantation areas comprises forming at least one standard pattern consisting of a first area and a second area for use in measuring resistance, implanting first and second conduction type impurity ions into the first and se... | 05/06/2008 |
| 7365429 | Semiconductor device and method for manufacturing the same A semiconductor device, comprising: a semiconductor substrate in which an integrated circuit is formed, the semiconductor substrate having an electrode electrically connected to the integrated circuit; a resin layer formed on a face in which the electrode of the sem... | 04/29/2008 |
| 7348210 | Post bump passivation for soft error protection A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passiv... | 03/25/2008 |
| 7344919 | Method for using gel package structure enhancing thermal dissipation between compressed printed circuit board and heat sink mechanical stiffener A MCM system board uses a stiffener arrangement to enhance mechanical, thermo and electrical properties by incorporating an LGA compression connector in a computer system. The present designs of large scale computing systems (LSCS) in IBM use a MCM that is attached ... | 03/18/2008 |
| 7335971 | Method for protecting encapsulated sensor structures using stack packaging A method of protecting a micro-mechanical sensor structure embedded in a micro-mechanical sensor chip, in which the micro-mechanical sensor structure is fabricated with a protective membrane, the micro-mechanical sensor chip is arranged so that a surface of the prot... | 02/26/2008 |
| 7321166 | Wiring board having connecting wiring between electrode plane and connecting pad It is to provide a wiring board for a semiconductor integrated circuit package, which exhibits an excellent signal property and a high effect for decreasing the switching noise at the time of mounting an LSI of an area-array structure. In a multilayer wiring board f... | 01/22/2008 |
| 7297571 | Electrostatically actuated low response time power commutation micro-switches The field of the invention is that of microsystems of the electrostatically actuated microswitch type that are used in electronics to carry out switching functions, especially in the microwave field for mobile telephony and radars. The object of the invention is to ... | 11/20/2007 |
| 7291553 | Method for forming dual damascene with improved etch profiles A method for forming a dual damascene with improved profiles including providing a semiconductor process wafer including a dielectric insulating layer and an overlying hardmask layer; forming an uppermost layer of amorphous carbon substantially conformally over the ... | 11/06/2007 |
| 7285842 | Siloxane epoxy polymers as metal diffusion barriers to reduce electromigration Structures employing siloxane epoxy polymers as diffusion barriers adjacent conductive metal layers are disclosed. The siloxane epoxy polymers exhibit excellent adhesion to conductive metals, such as copper, and provide an increase in the electromigration lifetime o... | 10/23/2007 |
| 7282434 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor integrated circuit device is provided including forming a first insulating film comprised of fluorine-containing silicon oxide over a main surface of a semiconductor substrate is formed together with forming a second insulat... | 10/16/2007 |
| 7276387 | Castellation wafer level packaging of integrated circuit chips Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and i... | 10/02/2007 |
| 7274093 | Semiconductor device connector, semiconductor device carrier, semiconductor device socket using the same and probe card A semiconductor device carrier comprising; a carrier housing having a housing portion for accommodating a semiconductor device; an electrode sheet disposed in the carrier housing, having a front surface wiring conductively arranged on a front surface of an insulatio... | 09/25/2007 |
| 7262493 | System and method for mounting electrical devices In one embodiment an electronic device, such as an optical sensor, is attached to a substrate upon which wire logouts and, if desired, other components are constructed. A frame, or cover, is attached to the substrate surrounding the attached device. An aperture in t... | 08/28/2007 |
| 7262491 | Die pad for semiconductor packages and methods of making and using same A semiconductor device package comprising a semiconductor device and an electrically conductive lead frame at least partially covered by a molding compound. The electrically conductive lead frame includes a plurality of leads disposed proximate a perimeter of the pa... | 08/28/2007 |
| 7256501 | Semiconductor device and manufacturing method of the same In a semiconductor device having a package structure in which lead terminals connected to electrodes on both of the upper and lower surfaces of a semiconductor chip are exposed from both of the upper and lower surfaces and side surfaces of a sealing body formed of r... | 08/14/2007 |
| 7253509 | Semiconductor device, electronic card and pad rearrangement substrate A semiconductor device comprises a substrate, an external terminal provided on the substrate, an internal wiring pattern electrically connected to the external terminal, a semiconductor chip mounted on the substrate and electrically connected to the internal wiring ... | 08/07/2007 |
| 7253516 | Electronic device and carrier substrate for same Consistent with an example embodiment, an electronic device comprises an integrated circuit and a carrier substrate with a bottom and top conductive layer, and is provided with voltage supply, ground and signal transmission connections. In order to enable the use of... | 08/07/2007 |
| 7247943 | Integrated circuit with at least one bump In an integrated circuit (1) having a substrate (3) and having a signal-processing circuit (4) which is produced at a surface (8) of the substrate (3), there is provided on the substrate surface (8) a protective layer (12... | 07/24/2007 |
| 7245011 | Prevention of contamination on bonding pads of wafer during SMT A semiconductor device is disclosed for preventing contamination on its bonding pads during mounting an electronic component, such as surface mount device (SMD). The semiconductor device includes a semiconductor substrate, a plurality of jointing material and at lea... | 07/17/2007 |
| 7242082 | Stackable layer containing ball grid array package Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded togethe... | 07/10/2007 |
| 7229898 | Methods for fabricating a germanium on insulator wafer Improved fabrication processes for manufacturing GeOI type wafers are disclosed. In an implementation, a method for fabricating a germanium on insulator wafer includes providing a source substrate having a surface, at least a layer of germanium and a weakened area. ... | 06/12/2007 |
