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| Number | Title | Issue Date |
| 7435626 | Rearrangement sheet, semiconductor device and method of manufacturing thereof There are provided a semiconductor device construction having more degrees of design freedom of the semiconductor element than prior arts, and a method of manufacturing such device easily and at low cost. For this purpose, a rearrangement sheet is employed provided ... | 10/14/2008 |
| 7422914 | Fabrication method of semiconductor integrated circuit device A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulat... | 09/09/2008 |
| 7396775 | Method for manufacturing semiconductor device The present invention discloses improved method for manufacturing semiconductor device wherein the gate oxide films in the cell region, VPP peripheral circuit region and VDD peripheral circuit region are formed to have different thicknesses fro... | 07/08/2008 |
| 7341890 | Circuit board with built-in electronic component and method for manufacturing the same A circuit board with an built-in electronic component according to the present invention includes an insulating layer, a first wiring pattern provided on a first main surface of the insulating layer, a second wiring pattern provided on a second main surface differen... | 03/11/2008 |
| 7332736 | Article comprising gated field emission structures with centralized nanowires and method for making the same This invention provides novel methods of fabricating novel gated field emission structures that include aligned nanowire electron emitters (individually or in small groups) localized in central regions within gate apertures. It also provides novel devices using nano... | 02/19/2008 |
| 7309907 | Semiconductor device card methods of initializing checking the authenticity and the identity thereof The semiconductor device (11) of the invention comprises a circuit that is covered by a passivation structure. It is provided with a first security element (12) that comprises a local area of the passivation structure and which has a first impedance. P... | 12/18/2007 |
| 7303984 | Semiconductor substrate structure and processing method thereof A semiconductor substrate structure includes a substrate having a trench formed thereon, a polymer composite material supplied into the trench and an electroplate conductive layer formed on the substrate. Further, a semiconductor substrate processing method includes... | 12/04/2007 |
| 7297561 | Pattern for improved visual inspection of semiconductor devices A semiconductor structure is disclosed that enhances quality control inspection of device. The structure includes a substrate having at least one planar face, a first metal layer on the planar face, and covering some, but not all of the planar face in a first predet... | 11/20/2007 |
| 7294531 | Wafer level chip stack method Provided is a method by which differently-sized chips may be stacked at the wafer level. The wafer level chip stack method utilizes first and second wafer assemblies that support first and second wafers on adhesive tapes. One or both of the supported wafers may be s... | 11/13/2007 |
| 7291519 | Methods of forming transistor constructions The invention includes a non-volatile memory cell comprising a field effect transistor construction having a body region within a crystalline material. The body region includes a charge trapping region. The memory cell can be TFT-SOI based, and can be supported by a... | 11/06/2007 |
| 7253091 | Process for assembling three-dimensional systems on a chip and structure thus obtained A method for assembling an electronic system with a plurality of layers. Recesses in formed in one or more dielectric layers and electronic components are positioned within the recesses. One or more layers containing the components are placed on a host substrate con... | 08/07/2007 |
| 7242099 | Chip package with multiple chips connected by bumps A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pil... | 07/10/2007 |
| 7217595 | Sealed three dimensional metal bonded integrated circuits The invention provides a sealing layer that seals metal bonding structures between three dimensional bonded integrated circuits from a surrounding environment. A material may be applied to fill a volume between the bonded integrated circuits or seal the perimeter of... | 05/15/2007 |
| 7214568 | Semiconductor device configured for reducing post-fabrication damage A semiconductor device includes an IC die configured to reduce post-fabrication damage to the device. The IC die is formed such that at least a portion of one or more perimeter edges of the die are beveled by an etching process. The semiconductor device may include ... | 05/08/2007 |
| 7199449 | Wafer backside removal to complete through-holes and provide wafer singulation during the formation of a semiconductor device A method used to form a semiconductor device comprises processing a semiconductor wafer to include one or more vias or through-holes only partially etched into the wafer, and scribe marks only partially etched into the wafer which define a plurality of semiconductor... | 04/03/2007 |
| 7196466 | Organic Electroluminescence device suppressing brightness unevenness An electrode of the organic EL device includes a substantially rectangular electrode region that contacts an organic layer, a terminal section to which an external drive circuit is connected, and a conductive section that electrically connects the terminal section t... | 03/27/2007 |
| 7176072 | Strained silicon devices transfer to glass for display applications A method of fabricating strained silicon devices for transfer to glass for display applications includes preparing a wafer having a silicon substrate thereon; forming a relaxed SiGe layer on the silicon substrate; forming a strained silicon layer on the relaxed SiGe... | 02/13/2007 |
| 6924346 | Etch-stop resins Silicone resins comprising 5 to 50 mole % of (PhSiO3-x)/2(OH)x) units and 50 to 95 mole % (HSiO(3-x)/2(OH)x), where Ph is a phenyl group, x has a value of 0, 1 or 2 and wherein the cured silicone resin has a critical surfa... | 08/02/2005 |
| 6894392 | Scaleable integrated data processing device A scaleable integrated data processing device, particularly a microcomputer, comprises a processing unit with one or more processors and a storage unit with one or more memories. The data processing device is provided on a carrier substrate (S) and comprises mutuall... | 05/17/2005 |
| 6703075 | Wafer treating method for making adhesive dies A wafer treating method for making adhesive dies is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform a thermo-bonding adhesive film having B-stage pro... | 03/09/2004 |
| 6696318 | Methods for forming a die package Methods are provided for forming a die package. The method comprises stiffening a flexible substrate to provide a first flexibility of the flexible substrate, forming a mounting element on a first side of the flexible substrate, and mounting a first die o... | 02/24/2004 |
| 6693342 | Thin microelectronic substrates and methods of manufacture A microelectronic substrate and method for manufacture. In one embodiment, the microelectronic substrate includes a body having a first surface, a second surface facing a direction opposite from the first surface, and a plurality of voids in the body betw... | 02/17/2004 |
| 6687987 | Electro-fluidic assembly process for integration of electronic devices onto a substrate An electro-fluidic assembly process for integration of an electronic device or component onto a substrate which comprises: disposing components within a carrier fluid; attracting the components to an alignment sites on the substrate by means of electropho... | 02/10/2004 |
| 6682954 | Method for employing piggyback multiple die #3 A method for upgrading or remediating semiconductor devices utilizing a remediation, adaptation, modification or upgrade chip in a piggyback configuration with a primary bare chip to achieve an upgrade, modification or adaptation of the primary chip or re... | 01/27/2004 |
| 6682981 | Stress controlled dielectric integrated circuit fabrication General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a sem... | 01/27/2004 |
| 6683376 | Direct bonding of small parts and module of combined small parts without an intermediate layer inbetween A groove having a V-shaped section is provided on a bonding surface of an IC chip being as a first small part, while an elongate projection having a V-shaped section to engage with the groove of the first IC chip is provided on a corresponding portion of ... | 01/27/2004 |
| 6682955 | Stacked die module and techniques for forming a stacked die module A technique for forming die stacks. Specifically, a stacking tip is provided to facilitate the stacking of die in a desired configuration. A first die is picked up by the stacking tip. The first die is coated with an adhesive on the underside of the die. ... | 01/27/2004 |
| 6673650 | Multi chip semiconductor package and method of construction A multi-chip semiconductor package using a lead-on-chip lead frame. The lead-on-chip package places two or more lead-on-chip dice into one package that are either attached to their own lead-on-chip lead frame or are mounted to the same lead-on-chip lead f... | 01/06/2004 |
| 6674161 | Semiconductor stacked die devices Semiconductor devices and methods of forming semiconductor devices are described. In one embodiment, at least one conductive structure is formed within a plurality of semiconductor substrates. At least portions of one of the conductive structures have opp... | 01/06/2004 |
| 6675109 | Systems and methods for forming data storage devices Systems for assembling wafer stacks are provided. An embodiment of the system includes a vacuum chamber, a media deposition component and a wafer stack assembly component. The media deposition component is arranged within the vacuum chamber and is configu... | 01/06/2004 |
| 6670217 | Methods for forming a die package Methods are provided for forming a die package. The method comprises stiffening a flexible substrate to provide a first flexibility of the flexible substrate, forming a mounting element on a first side of the flexible substrate, and mounting a first side ... | 12/30/2003 |
| 6667225 | Wafer-bonding using solder and method of making the same A method is provided for forming a wafer stack. This may include providing a first wafer having a first plurality of metalized trenches on a surface of the first wafer. A second wafer may be provided having a second plurality of metalized trenches on a su... | 12/23/2003 |
| 6664132 | Method for producing three-dimensional circuits In a method of producing three-dimensional circuits, a first and a second substrate are first provided, each of said substrates having arranged therein a plurality of components which have been tested with regard to their operability. The second substrate... | 12/16/2003 |
| 6658727 | Method for assembling die package A method of assembling a multi-chip module does not necessitate more the one pass through a die attach machine. The method involves attaching a smaller die to a larger die without using a die attach machine. The larger die may be attached to a support str... | 12/09/2003 |
| 6657290 | Semiconductor device having insulation layer and adhesion layer between chip lamination A semiconductor device includes a first semiconductor chip and a second semiconductor chip which are laminated on a substrate, wherein electrode terminals which are provided on each of the semiconductor chips are electrically connected to the substrate by... | 12/02/2003 |
| 6653208 | Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing A semiconductor device wafer-on-support wafer package comprising a plurality of segmentable chip-scale packages and method of constructing, burning-in, and testing same is disclosed. The wafer-on-wafer package can be burned-in and tested at the wafer leve... | 11/25/2003 |
| 6652808 | Methods for the electronic assembly and fabrication of devices Methods provide for electric field assisted self-assembly of functionalized programmable nucleic acids, nucleic acid modified structures, and other selective affinity or binding moieties as building blocks for: creating molecular electronic and photonic m... | 11/25/2003 |
| 6645828 | In situ plasma wafer bonding method A method for chemically bonding semiconductor wafers and other materials to one another without exposing wafers to wet environments, and a bonding chamber for in situ plasma bonding are disclosed. The in situ plasma bonding chamber allows plasma activatio... | 11/11/2003 |
| 6638482 | Reconfigurable detection and analysis apparatus and method Methods and apparatus for use of a stacked, reconfigurable system is provided. The stacked, reconfigurable system includes an inlet for receipt of a sample, a first chamber defined by a bottom support, an intermediate member, and a first spacer, the first... | 10/28/2003 |
| 6636334 | Semiconductor device having high-density packaging thereof A semiconductor device comprises a semiconductor IC chip provided with bond pads on its first surface, a wiring board provided with a through hole extending between the opposite surfaces thereof, conductive members electrically connecting the bond pads of... | 10/21/2003 |
