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| Number | Title | Issue Date |
| 7425754 | Structure and method of self-aligned bipolar transistor having tapered collector A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface havi... | 09/16/2008 |
| 7335547 | Method for effective BiCMOS process integration According to an exemplary embodiment, a method for integrating bipolar and CMOS devices on a substrate, where the substrate includes bipolar and CMOS regions and has a sacrificial oxide layer situated thereon, includes removing a portion of the sacrificial oxide lay... | 02/26/2008 |
| 7303968 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 12/04/2007 |
| 7256445 | Fabrication of an EEPROM cell with emitter-polysilicon source/drain regions An EEPROM memory cell uses an emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage of the wells. The wells are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approxi... | 08/14/2007 |
| 7232733 | Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a transistor by forming a gate over a semiconductor substrate. The method of ... | 06/19/2007 |
| 7205657 | Complimentary lateral nitride transistors A semiconductor device which includes a laterally extending stack of laterally adjacent conductive semiconductor regions formed over a support surface of a substrate, and a method for fabricating the device. ... | 04/17/2007 |
| 7091597 | Power supply device A power supply device includes a control IC fabricated by a bipolar process and a power supply element fabricated by a MOS process, both of them die-bonded on a leadframe, and with a chip edge of one of them kept in intimate contact with a chip edge of the other. Th... | 08/15/2006 |
| 6703685 | Super self-aligned collector device for mono-and hetero bipolar junction transistors The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is dispo... | 03/09/2004 |
| 6700144 | Semiconductor device and method for manufacturing the same A semiconductor device includes the following: a semiconductor substrate of a first conduction type; an intrinsic semiconductor layer of the first conduction type formed on the semiconductor substrate; a first semiconductor layer of a second conduction ty... | 03/02/2004 |
| 6696342 | Small emitter and base-collector bi-polar transistor In a high speed BJT device, the method for producing the device includes forming a self-aligned BJT through the use of a single mask by making use of a single layer of polysilicon. The method includes forming a window in the polysilicon to define a base p... | 02/24/2004 |
| 6670229 | Bipolar transistor produced using processes compatible with those employed in the manufacture of MOS device A bipolar transistor is produced by processes employed in the manufacture of CMOS nonvolatile memory devices, and is part of an integrated circuit. The integrated circuit includes a semiconductor substrate having a first type of conductivity, a PMOS trans... | 12/30/2003 |
| 6670228 | Method of fabricating a polysilicon capacitor utilizing FET and bipolar base polysilicon layers A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said cap... | 12/30/2003 |
| 6667521 | Bipolar transistor with raised extrinsic base fabricated in an integrated BiCMOS circuit A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is ... | 12/23/2003 |
| 6667202 | Semiconductor device and method for making the same A semiconductor device which has: a bipolar transistor having a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the su... | 12/23/2003 |
| 6656811 | Carbide emitter mask etch stop Bipolar transistors and methods for fabricating bipolar transistors are disclosed wherein an emitter-base dielectric stack is formed between emitter and base structures, comprising a carbide layer situated between first and second oxide layers. The carbid... | 12/02/2003 |
| 6657281 | Bipolar transistor with a low K material in emitter base spacer regions The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the ba... | 12/02/2003 |
| 6656815 | Process for implanting a deep subcollector with self-aligned photo registration marks A method of forming a BiCMOS device having a deep subcollector region and self-aligned alignment marks is provided. The inventive method includes the steps of: (a) lithographically forming a first patterned layer comprising a thick dielectric material on ... | 12/02/2003 |
| 6649487 | Method of manufacturing semiconductor integrated circuit device A method of manufacturing a semiconductor integrated circuit device according to this invention, comprises a step of forming in a semiconductor substrate a deep groove for trench isolation with an aspect ratio of greater than 1, a step of burying a first ... | 11/18/2003 |
| 6649982 | Integration of bipolar and CMOS devices for sub-0.1 micrometer transistors Form a semiconductor device with dielectric, isolation structures in a top surface of a silicon semiconductor substrate, separating the substrate into emitter, NMOS and PMOS areas. Form a gate oxide layer above the isolation structures on the top surface ... | 11/18/2003 |
| 6649983 | Vertical bipolar transistor formed using CMOS processes A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect device. The implantation steps form an n-well, a p-well region, a pocket base region and an emitter... | 11/18/2003 |
| 6646311 | Vertical bipolar transistor formed using CMOS processes A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect device. The implantation steps form an n-well, a channel stop p-well region and emitter region whic... | 11/11/2003 |
| 6646320 | Method of forming contact to poly-filled trench isolation region Existing polysilicon emitter technology is used to contact poly fill in a trench isolation structure. A standard single poly emitter window process is followed. An "emitter window" is masked directly over the polysilicon trench fill. Heavily doped single ... | 11/11/2003 |
| 6638806 | Semiconductor device and method of fabricating the same A collector region is formed on a semiconductor substrate. An emitter electrode, an external base electrode and a gate electrode are formed on the semiconductor substrate. The position of the interface between the gate electrode and the semiconductor subs... | 10/28/2003 |
| 6633069 | Semiconductor device A bipolar transistor has metal silicide as a base lead-out electrode instead of conventional polysilicon, and the metal silicide film extends to an edge of an etching stopper layer, to reduce an emitter resistance and restrain an occurrence of an emitter ... | 10/14/2003 |
| 6630377 | Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reach... | 10/07/2003 |
| 6627972 | Vertical bipolar transistor The invention relates to a vertical bipolar transistor and a method for the production thereof. The aim of the invention is to produce a vertical bipolar transistor and to disclose a method for the production thereof, whereby excellent high frequency prop... | 09/30/2003 |
| 6617647 | Insulated gate semiconductor device and method of manufacturing the same Dot-pattern-like impurity regions 104 are artificially and locally formed on a channel forming region 103. The impurity regions 104 restrain the expansion of a drain side depletion layer toward the channel forming region 103 to prevent the short channel e... | 09/09/2003 |
| 6611044 | Lateral bipolar transistor and method of making same A lateral bipolar transistor for an intergrated circuit is provided that maintains a high current gain and high frequency capability without sacrificing high Early voltage. More particularly, a lateral bipolar transistor is formed on an integrated circuit... | 08/26/2003 |
| 6607960 | Bipolar transistor manufacturing method A method of manufacturing a bipolar transistor in a P-type substrate, including the steps of forming in the substrate a first N-type area; forming by epitaxy a first silicon layer; forming in this first layer, and substantially above the first area a seco... | 08/19/2003 |
| 6602747 | Method for fabricating bipolar complementary metal oxide semiconductor (BiCMOS) device structure Within both a method for fabricating a bipolar transistor device and a method for fabricating a BiCMOS device there is: (1) formed contacting a base contact region a polysilicon base contact of a second polarity; and (2) formed contacting an emitter conta... | 08/05/2003 |
| 6600199 | Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity The preferred embodiment of the present invention provides a buried layer that improves the latch up immunity of digital devices while providing isolation structures that provide noise isolation for both the digital and analog devices. The buried layer of... | 07/29/2003 |
| 6593178 | BI-CMOS integrated circuit The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. F... | 07/15/2003 |
| 6586297 | Method for integrating a metastable base into a high-performance HBT and related structure According to one exemplary embodiment, a heterojunction bipolar transistor is fabricated by forming a metastable epitaxial silicon-germaniuim base on a collector. The metastable epitaxial silicon-gernaniuim base, for example, may have a concentration of g... | 07/01/2003 |
| 6586298 | Method of forming high performance bipolar transistor A method of fabricating a bipolar transistor structure is provided in which a blanket silicon-germanium (SiGe) film is used in a self-aligned manner to form the active base region of the bipolar device, thereby eliminating the need for a complicated selec... | 07/01/2003 |
| 6576507 | Selectively removable filler layer for BiCMOS process The present invention is intended for use on BiCMOS technology where the BJTs are formed after the FETs. A thin FET protection layer 26 is deposited on the raised and recessed regions 28 of the semiconductor substrate 10. A selectively removable filler la... | 06/10/2003 |
| 6576535 | Carbon doped epitaxial layer for high speed CB-CMOS A method for fabricating a high speed complementary bipolar/CMOS device is disclosed which enables the forming of a silicon epitaxial layer in a PNP transistor having carbon incorporated therein to suppress boron up-diffusion from lower heavily boron-dope... | 06/10/2003 |
| 6569744 | Method of converting a metal oxide semiconductor transistor into a bipolar transistor The present invention provides a method of manufacturing a bipolar transistor. The method includes producing an opening in a dielectric layer located over a substrate and forming a collector in the substrate by implanting a first dopant through the openin... | 05/27/2003 |
| 6570242 | Bipolar transistor with high breakdown voltage collector A transistor that includes a doped buried region 320 within a semiconductor body 300, 340. The doped buried region includes a portion having a first thickness 348 and a second thickness, the first thickness being less than the second thickness. In one emb... | 05/27/2003 |
| 6566217 | Manufacturing process for semiconductor device A manufacturing process for a semiconductor device including a semiconductor memory region and a peripheral circuit region including bipolar transistors, in which a plurality of bipolar transistors with characteristics different from each other are effect... | 05/20/2003 |
| 6548873 | Semiconductor device and manufacturing method of the same A semiconductor device causes less element characteristic fluctuation and hardly causes parasitic actions even when a wire having a barrier metal made of a titanium material is provided. The semiconductor device includes a MOS transistor provided on the s... | 04/15/2003 |
