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| Number | Title | Issue Date |
| 6278143 | Semiconductor device with bipolar and J-FET transistors In a semiconductor device by a complex-type bipolar transistor device in which a junction-type field effect transistor is connected to a bipolar transistor, to make it possible to ensure a good and stable characteristic of the bipolar transistor without i... | 08/21/2001 |
| 6144077 | Semiconductor device comprising a bipolar transistor A semiconductor device is provided in its base region with an emitter region consisting of a p-type first impurity layer having a first impurity concentration peak at a first depth and a p-type second impurity layer having an impurity concentration peak a... | 11/07/2000 |
| 5912479 | Heterojunction bipolar semiconductor device A semiconductor device includes a heterojunction bipolar transistor and a junction gate type field effect transistor which are formed on a semiconductor base. A base region and graft base regions of the heterojunction bipolar transistor, and a channel reg... | 06/15/1999 |
| 5652153 | Method of making JFET structures for semiconductor devices with complementary bipolar transistors A semiconductor device may include complementary NPN and PNP transistors and a JFET that is formed in the same steps as used to form the transistors. The bottom gate of the JFET and the back collector layer of the PNP transistor are doped and up-diffused ... | 07/29/1997 |
| 5624854 | Method of formation of bipolar transistor having reduced parasitic capacitance Vertically stacked regions of n-type and p-type conductivity are formed around bipolar and field effect transistors to reduce parasitic capacitance between the semiconductor device and surrounding well regions. Under reverse bias a portion of the vertical... | 04/29/1997 |
| 5504363 | Semiconductor device Vertically stacked regions of n-type and p-type conductivity are formed around bipolar and field effect transistors to reduce parasitic capacitance between the semiconductor device and surrounding well regions. Under reverse bias a portion of the vertical... | 04/02/1996 |
| 5488005 | Process for manufacturing an offset gate structure thin film transistor A process for manufacturing an offset gate structure thin film transistor which includes the steps of forming a first semiconductor layer, e.g., an active layer made of amorphous silicon or polysilicon, on a major surface of a substrate, e.g., a glass sub... | 01/30/1996 |
| 5466621 | Method of manufacturing a semiconductor device having silicon islands A semiconductor device such as FET or charge coupled device, having a channel or a charge coupled portion provided in a thin semiconductor layer which is nearly perpendicular to the substrate and to which the necessary electrode such as the gate electrode... | 11/14/1995 |
| 5391504 | Method for producing integrated quasi-complementary bipolar transistors and field effect transistors Generally, and in one form of the invention, an integrated circuit comprising a bipolar transistor and a field effect transistor, wherein a channel of the field effect transistor and a base of the bipolar transistor are formed from a base epitaxial layer ... | 02/21/1995 |
| 5356821 | Method for manufacturing semiconductor integrated circuit device A semiconductor integrated circuit according to the present invention comprises a semiconductor substrate, a plurality of MOS field effect transistors each formed on a surface region of the semiconductor substrate and having source and drain regions, a ga... | 10/18/1994 |
| 5352617 | Method for manufacturing Bi-CMOS transistor devices A method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor is disclosed, which comprises covering the bipolar transistor formation region with a gate insulating film and also with a first gate formation material at t... | 10/04/1994 |
| 5348907 | Method of fabricating of semiconductor device by forming two electrically insulated wells of the same type electroconductivity on semiconductor substrate A fabrication method of a semiconductor device in which the characteristic deterioration of the device due to electric charges generating in the fabrication process can be prevented. A first well of a first electroconductive type is formed on a semiconduc... | 09/20/1994 |
| 5346834 | Method for manufacturing a semiconductor device and a semiconductor memory device An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the s... | 09/13/1994 |
| 5342480 | Method of manufacturing a semiconductor integrated circuit device An isolation and flattening technique for a semiconductor substrate having active devices, such as a bipolar transistor, and a MISFET, formed thereon, is disclosed. The technique includes forming grooves, to the main surface of a non-active region of a se... | 08/30/1994 |
| 5280188 | Method of manufacturing a semiconductor integrated circuit device having at least one bipolar transistor and a plurality of MOS transistors A semiconductor device includes a bipolar transistor and an IIL element fabricated on a single wafer. The emitter region of the bipolar transistor is formed by diffusing the impurity of an impurity layer formed in contact with the base region therein. The... | 01/18/1994 |
| 5270249 | Fabrication process of a semiconductor device having a reduced parasitic capacitance A fabrication process of a semiconductor device comprises the steps of providing a temporary layer on a semiconductor substrate, patterning the temporary layer to form a temporary protection pattern on the semiconductor substrate such that the temporary p... | 12/14/1993 |
| 5254864 | Semiconductor device A semiconductor device wherein a bipolar transistor and a junction type field effect transistor which has a high voltage resisting property and a high mutual conductance are formed into a single chip to reduce the cost. A bipolar transistor formation regi... | 10/19/1993 |
| 5246871 | Method of manufacturing a semiconductor device comprising a control circuit and a power stage with a vertical current flow, integrated in monolithic form on a single chip The problems normally linked to the creation of a power stage using BJT transistors are overcome realizing the power stage with BMFET transistors.... | 09/21/1993 |
| 5153697 | Integrated circuit that combines multi-epitaxial power transistors with logic/analog devices, and a process to produce same An integrated circuit is formed on an N-type semiconductor wafer having a first N-type epitaxial layer on the substrate, a P-type epitaxial layer over the first N-type epitaxial layer, and a second N-type epitaxial layer over the P-type epitaxial layer. T... | 10/06/1992 |
| 5144408 | Semiconductor integrated circuit device and method of manufacturing the same A semiconductor device includes a bipolar transistor and an IIL element fabricated on a single wafer. The emitter region of the bipolar transistor is formed by diffusing the impurity of an impurity layer formed in contact with the base region therein. The... | 09/01/1992 |
| 5119161 | Semiconductor device comprising a control circuit and a power stage with a vertical current flow, integrated in monolithic form on a single chip The problems normally linked to the creation of a power stage using BJT transistors are overcome realizing the power stage with BMFET transistors.... | 06/02/1992 |
| 5115289 | Semiconductor device and semiconductor memory device A semiconductor device, such as an FET or a charge coupled device, is provided having a channel or a charge coupled portion formed in a thin semiconductor layer which is substantially perpendicular to the substrate. Necessary electrodes, such as the gate ... | 05/19/1992 |
| 5104817 | Method of forming bipolar transistor with integral base emitter load resistor The described embodiments of the present invention provide a bipolar transistor using an integrated field effect load device with one end of the load device integrally formed with the base of the transistor. The gate of the load device is connected to the... | 04/14/1992 |
| 5077228 | Process for simultaneous formation of trench contact and vertical transistor gate and structure The described embodiments of the present invention provide structures and methods for fabricating the structures which provide compact contact from the surface of an integrated circuit to a buried layer formed in conjunction with a vertical gate extending... | 12/31/1991 |
| 5034337 | Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices A process of fabricating semiconductor devices involving plural epitaxial layer growth steps.... | 07/23/1991 |
| 5006476 | Transistor manufacturing process using three-step base doping In a transistor fabrication process, the use of a three-step base doping technique enables the characteristics of a vertical bipolar transistor to be controllably reproduced at highly optimal values from run to run. Insulating spacers (52A) are employed i... | 04/09/1991 |
| 4980303 | Manufacturing method of a Bi-MIS semiconductor device With a trend toward higher operation speed and higher gain of a Bi-MIS semiconductor device, wherein a bipolar transistor and a MIS FET are formed on the same silicon substrate, a wide bandgap material such as silicon carbide or micro-crystalline silicon ... | 12/25/1990 |
| 4949137 | Semiconductor device A semiconductor device comprises a heavily doped semiconductor layer exposed to both principal surfaces of a semiconductor substrate, a semiconductor element such as a diode, a bipolar transistor, and a MOS transistor, etc. formed on one principal surface... | 08/14/1990 |
| 4939099 | Process for fabricating isolated vertical bipolar and JFET transistors A unified process flow for the fabrication of an isolated vertical PNP (VPNP) transistor, a junction field effect transistor (JFET) and a metal/nitride/polysilicon capacitor includes the simultaneous fabrication of deep junction isolation regions (36, 121... | 07/03/1990 |
| 4935800 | Semiconductor integrated circuit This invention discloses a semiconductor integrated circuit in which an analog circuit and a digital circuit are formed on a single chip. The semiconductor integrated circuit includes a p-type semiconductor region, an n+ -type buried region for... | 06/19/1990 |
| 4898839 | Semiconductor integrated circuit and manufacturing method therefor A method of manufacturing a semiconductor integrated circuit comprises the steps of: forming an epitaxial layer covering a semiconductor substrate and buried layers; forming isolation regions dividing the epitaxial layer into a plurality of islands; formi... | 02/06/1990 |
| 4808547 | Method of fabrication of high voltage IC bopolar transistors operable to BVCBO A high voltage bipolar and JFET have their gate and base connected and source and collector connected and the appropriate geometry for the bipolar to operate to its BVCBO limit. The collector and channel regions have the same depth and impurity... | 02/28/1989 |
| 4783423 | Fabrication of a semiconductor device containing deep emitter and another transistor with shallow doped region A semiconductor device comprising a deep emitter region having a high withstand voltage between the collector and emitter VCEO and another element comprising a doped region which should be substantially shallower than the deep emitter region, m... | 11/08/1988 |
| 4729008 | High voltage IC bipolar transistors operable to BVCBO and method of fabrication A high voltage bipolar and JFET have their gate and base connected and source and collector connected and the appropriate geometry for the bipolar to operate to its BVCBO limit. The collector and channel regions have the same depth and impurity... | 03/01/1988 |
| 4553318 | Method of making integrated PNP and NPN bipolar transistors and junction field effect transistor A semiconductor device and method for making same having three transistors, NPN, PNP, and junction field effect, concurrently formed integral to a common semiconductor device.... | 11/19/1985 |
| 4550490 | Monolithic integrated circuit A method of producing an integrated insulated-gate field-effect transistor with an increased breakdown voltage provides in that at least one of the two zones, i.e. the source zone and/or the drain zone is surrounded by a relatively high-ohmic partial zone... | 11/05/1985 |
| 4546370 | Monolithic integration of logic, control and high voltage interface circuitry Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, using various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, a... | 10/08/1985 |
| 4497106 | Semiconductor device and a method of manufacturing the same A semiconductor device comprising at least one bipolar transistor and at least one MIS FET integrated in a single semiconductor substrate, has an electrode for each region of the bipolar transistor and the MIS FET. Each electrode has the same conductivity... | 02/05/1985 |
| 4481707 | Method for the fabrication of dielectric isolated junction field effect transistor and PNP transistor The process of fabricating a dielectrically isolated junction field effect transistor and a PNP transistor on a common substrate. An epitaxially layer is deposited on the base substrate to form the channel region of the junction field effect transistor. I... | 11/13/1984 |
| 4443933 | Utilizing multi-layer mask to define isolation and device zones in a semiconductor substrate A method is disclosed for the self-aligned manufacture of a semiconductor device having island insulation obtained by thermal oxidation. An insulating layer (preferably of silicon oxide), a layer of silicon nitride, and a layer preferably of aluminum oxid... | 04/24/1984 |
