Class 257/E21.693 - For vertical channel (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.692. This subclass
No. of patents: 78
Last issue date: 11/27/2007

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Number	Title	Issue Date
7301804	NROM memory cell, memory array, related devices and methods An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing...	11/27/2007
7268379	Memory cell and method for manufacturing the same The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together def...	09/11/2007
7190019	Integrated circuits with openings that allow electrical contact to conductive features having self-aligned edges A widened contact area (170X) of a conductive feature (170) is formed by means of self-alignment between an edge (170E2) of the conductive feature and an edge (140E) of another feature (140). The other feature (“first feat...	03/13/2007
7119384	Field effect transistor and method for fabricating it The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channe...	10/10/2006
7112832	Transistor having multiple channels A transistor (10) overlies a substrate (12) and has a plurality of overlying channels (72, 74, 76) that are formed in a stacked arrangement. A continuous gate (60) material surrounds each of the channels. Each of the channels is coupled t...	09/26/2006
7087950	Flash memory cell, flash memory device and manufacturing method thereof The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source-/drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said ch...	08/08/2006
6937513	Integrated NAND and nor-type flash memory device and method of using the same A semiconductor memory device is provided as well as a method for operating the semiconductor memory device. The memory device includes a NOR array of memory cells and a NAND array of memory cells configured on the same monolithic semiconductor substrate. Each cell ...	08/30/2005
6696724	Two-transistor flash cell A semiconductor device comprising a non-volatile memory cell (20; 200) for storing a bit, arranged in a semiconductor substrate (21) containing a first dopant type, the memory cell including a drain (24) in the substrate (21), a floating gate (29), a cont...	02/24/2004
6680508	Vertical floating gate transistor A floating gate transistor has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The ...	01/20/2004
6677204	Multigate semiconductor device with vertical channel current and method of fabrication The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first ch...	01/13/2004
6639268	Flash memory with ultra thin vertical body transistors Structures and method for Flash memory with ultra thin vertical body transistors are provided. The Flash memory includes an array of memory cells including floating gate transistors. Each floating gate transistor includes a pillar extending outwardly from...	10/28/2003
6630708	Non-volatile memory and method for fabricating the same A non-volatile memory includes a substrate: a floating gate electrode and a control gate electrode formed on the substrate; and an active layer formed around the control gate and the floating gate. The active layer has source and drain and a channel layer...	10/07/2003
6583466	Vertical split gate flash memory device in an orthogonal array of rows and columns with devices in columns having shared source regions A vertical transistor memory device includes FET cells formed in rows and columns with the rows orthogonally arranged relative to the columns. Several cells in a single row have a common source region and adjacent cells have a common drain region FOX regi...	06/24/2003
6555870	Nonvolatile semiconductor memory device and method for producing same A groove 11 is formed in a semiconductor substrate 10. A source region 12 is formed on the bottom of the groove 11 on the side of the surface of the semiconductor substrate 10. A drain region 14 is formed in a portion, in which the groove 11 is not formed...	04/29/2003
6548856	Vertical stacked gate flash memory device A method of forming a vertical transistor memory device comprises the following process steps. Before forming the trenches, FOX regions are formed between the rows. Then form a set of trenches with sidewalls and a bottom in a semiconductor substrate with ...	04/15/2003
6541815	High-density dual-cell flash memory structure A 2F2 flash memory cell structure and a method of fabricating the same are provided. The 2F2 flash memory cell structure includes a Si-containing substrate having a plurality of trenches formed therein. Each trench has sidewalls that...	04/01/2003
6498030	Surrounding-gate flash memory having a self-aligned control gate The structure of a flash memory is described. Device isolation structures are located on the substrate. Sources are provided on the top layer of the substrate between two device isolation structures. Tunneling oxide layers are provided at both ends of the...	12/24/2002
6486027	Field programmable logic arrays with vertical transistors A field programmable logic array with vertical transistors having single or split control lines is used to provide logical combinations responsive to an input signal. The transistor is a field-effect transistor (FET) having an electrically isolated (float...	11/26/2002
6465838	Surrounding-gate flash memory having a self-aligned control gate The structure of a flash memory is described. Device isolation structures are located on the substrate. Sources are provided on the top layer of the substrate between two device isolation structures. Tunneling oxide layers are provided at both ends of the...	10/15/2002
6448135	Semiconductor device and method of fabricating same The present invention relates to a nonvolatile semiconductor device using a vertical channel semiconductor device and a method of fabricating the same. The method starts with forming an insulator for device isolating having a depth D in a semiconductor su...	09/10/2002
6440801	Structure for folded architecture pillar memory cell A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the oth...	08/27/2002
6437397	Flash memory cell with vertically oriented channel A vertical memory device on a silicon semiconductor substrate is formed by the following steps. Form an array of isolation silicon oxide structures on the surface of the silicon semiconductor substrate. Form a floating gate trench in the silicon semicondu...	08/20/2002
6391719	Method of manufacture of vertical split gate flash memory device A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold impl...	05/21/2002
6391721	Non-volatile semiconductor memory device having vertical transistors and fabrication method therefor A non-volatile semiconductor memory cell array including an MOS transistor having a vertical channel along an inside wall of a trench in each cell is developed for high density integration and high speed operations. One aspect of the invention is that the...	05/21/2002
6383871	Method of forming multiple oxide thicknesses for merged memory and logic applications Improved methods and structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, improved methods and structures are provided for multiple gate oxide thicknesses on a single chip wherein the chip can include circuitry ...	05/07/2002
6377070	In-service programmable logic arrays with ultra thin vertical body transistors Structures and methods for in-service programmable logic arrays with ultra thin vertical body transistors are provided. The in-service programmable logic array includes a first logic plane that receives a number of input signals. The first logic plane has...	04/23/2002
6316315	Method for fabricating a memory cell having a MOS transistor A memory cell has a vertical MOS transistor which contains a first electrically insulated gate electrode and a second gate electrode. The second gate electrode is partially disposed in a trench whose sidewall is adjoined by the MOS transistor. The first g...	11/13/2001
6255689	Flash memory structure and method of manufacture A flash memory cell structure and its method of manufacture. The flash memory cell has a vertical configuration. An opening and then a trench are formed in a substrate by etching. The trench (defined as the recessed section of the substrate) is used for f...	07/03/2001
6238976	Method for forming high density flash memory A method of forming a memory array. The method includes forming a plurality of first conductivity type semiconductor pillars upon a substrate. Each pillar has a top and a side surface. The method includes forming a plurality of first source/drain regions,...	05/29/2001
6239465	Non-volatile semiconductor memory device having vertical transistors with the floating and control gates in a trench and fabrication method therefor A non-volatile semiconductor memory cell array including an MOS transistor having a vertical channel along an inside wall of a trench in each cell is developed for high density integration and high speed operations. One aspect of the invention is that the...	05/29/2001
6211015	Ultra high density flash memory having vertically stacked devices An ultra high density flash EEPROM provides increased nonvolatile storage capacity. A memory array includes densely packed memory cells, each cell having a pillar of semiconductor material that extends outwardly from a working surface of a substrate. The ...	04/03/2001
6198125	Semiconductor device and method of fabricating same The present invention relates to a nonvolatile semiconductor device using a vertical channel semiconductor device and a method of fabricating the same. The method starts with forming an insulator for device isolating having a depth D in a semiconductor su...	03/06/2001
6191459	Electrically programmable memory cell array, using charge carrier traps and insulation trenches An electrically programmable memory cell array is formed of memory cells, which include a vertical MOS transistor. The MOS transistor has a gate dielectric of a material with charge carrier traps. The memory cells are disposed along opposite edges of stri...	02/20/2001
6157060	High density integrated semiconductor memory and method for producing the memory The high density integrated semiconductor memory has an EPROM cell in the form of a pillar. The cell has a floating gate and a control gate. The EPROM cell is dimensioned so thin that it is fully depleted. The control gate of the preferred split gate flas...	12/05/2000
6143636	High density flash memory A high density flash EEPROM provides increased nonvolatile storage capacity. A memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for two vertical floating gate transistors...	11/07/2000
6124729	Field programmable logic arrays with vertical transistors A field programmable logic array with vertical transistors having single or split control lines is used to provide logical combinations responsive to an input signal. The transistor is a field-effect transistor (FET) having an electrically isolated (float...	09/26/2000
6108239	High-density nonvolatile memory cell A compact nonvolatile programmable memory cell. The memory cell has a floating gate (118), control gate (123), drain (108), and source regions (112). The memory cell is an electrically erasable programmable read only memory (EEPROM) cell or a Flash memory...	08/22/2000
6093606	Method of manufacture of vertical stacked gate flash memory device A method of forming a vertical transistor memory device comprises the following process steps. Before forming the trenches, FOX regions are formed between the rows. Then form a set of trenches with sidewalls and a bottom in a semiconductor substrate with ...	07/25/2000
6091102	High-density nonvolatile memory cell A compact nonvolatile programmable memory cell. The memory cell has a floating gate (118), control gate (123), drain (108), and source regions (112). The memory cell is an electrically erasable programmable read only memory (EEPROM) cell or a Flash memory...	07/18/2000
6087222	Method of manufacture of vertical split gate flash memory device A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold impl...	07/11/2000

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Class 257/E21.693 - For vertical channel (EPO)