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| Number | Title | Issue Date |
| 7439133 | Memory structure and method of manufacturing a memory array A memory structure formed between two doping regions in a semiconductor substrate includes two conductive blocks functioning as floating gates formed at two sides of a first conductive line functioning as a select gat and insulated from the first conductive line wit... | 10/21/2008 |
| 7399672 | Methods of forming nonvolatile memory devices Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semicondu... | 07/15/2008 |
| 7391073 | Non-volatile memory structure and method of fabricating non-volatile memory A method of fabricating a non-volatile memory is described. A substrate having a tunneling layer and a floating gate layer thereon is provided. A mask layer is formed on the floating gate. The mask layer has openings that expose a portion of the floating gate layer.... | 06/24/2008 |
| 7390749 | Self-aligned pitch reduction A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a se... | 06/24/2008 |
| 7384843 | Method of fabricating flash memory device including control gate extensions A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating ... | 06/10/2008 |
| 7378315 | Method for fabricating semiconductor device A method for fabricating a semiconductor device for a system on chip (SOC) for embodying a transistor for a logic device, an electrical erasable programmable read only memory (EEPROM) cell and a flash memory cell in one chip is provided. Floating gates of the EEPROM... | 05/27/2008 |
| 7351630 | Method of manufacturing flash memory device A method of manufacturing a flash memory device, including the steps of forming a gate on a semiconductor substrate in which a cell region, a source selection line region, and a drain selection line region are defined and then forming spacers on sidewalls of the gat... | 04/01/2008 |
| 7314803 | Method for producing a semiconductor structure In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of g... | 01/01/2008 |
| 7312503 | Semiconductor memory device including MOS transistors each having a floating gate and a control gate A semiconductor memory device includes a plurality of memory cells, a plurality of local bit lines, a global bit line, a first switch element, and a holding circuit. The memory cell includes first and second MOS transistors. The first MOS transistor has a charge acc... | 12/25/2007 |
| 7256086 | Trench lateral power MOSFET and a method of manufacturing the same A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional... | 08/14/2007 |
| 7253031 | Semiconductor device and manufacturing method thereof A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n | 08/07/2007 |
| 7253055 | Pillar cell flash memory technology An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon fl... | 08/07/2007 |
| 7235823 | Source side injection storage device with spacer gates and method therefor A storage device structure (10) has two bits of storage per control gate (34) and uses source side injection (SSI) to provide lower programming current. A control gate (34) overlies a drain electrode formed by a doped region (22) that is ... | 06/26/2007 |
| 7176086 | Interconnecting conductive layers of memory devices Field-effect transistors, select gates, and select lines have first and second conductive layers separated by an interlayer dielectric layer. A conductive strap is disposed on either side of the first and second conductive layers. Each strap electrically interconnec... | 02/13/2007 |
| 7122430 | Nonvolatile semiconductor memory and manufacturing method for the same The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-elect... | 10/17/2006 |
| 6703658 | Non-volatile semiconductor memory device and its manufacturing method In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a fi... | 03/09/2004 |
| 6630707 | Semiconductor device including logic circuit and memory circuit The semiconductor device with its primary bit line and secondary bit lines, according to the present invention, is capable of being accessed at a high speed. In this semiconductor device, any one of a plurality of secondary bit lines is selectively connec... | 10/07/2003 |
| 6624015 | Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions The manufacturing method comprises, in sequence, the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions... | 09/23/2003 |
| 6593188 | Non-volatile memory device having a silicide layer and fabrication method thereof A non-volatile memory device and a fabrication method thereof are provided. A first polysilicon layer, an inter-gate dielectric layer, a second polysilicon layer and a capping layer are stacked sequentially. A first opening is formed through the inter-gat... | 07/15/2003 |
| 6586805 | Non-volatile semiconductor memory device In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a fi... | 07/01/2003 |
| 6579762 | Nonvolatile semiconductor device having a memory cells each of which is constituted of a memory transistor and a selection transistor A tunnel oxide film 120, a first polysilicon layer 164, a poly--poly insulating film 132 and a second polysilicon layer 166 are formed on a semiconductor substrate in a memory cell area. After that, with two photo resists 168-S and 168-M as a mask, patter... | 06/17/2003 |
| 6573130 | Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors A process that provides for the manufacture of LV transistors with salicidated junctions on first areas of a substrate, HV transistors on second areas, and memory cells on third areas. The process includes forming LV oxide regions and LV gate regions on t... | 06/03/2003 |
| 6534355 | Method of manufacturing a flash memory having a select transistor According to the present invention, there is disclosed a 2-transistors type flash memory, wherein a memory-transistor is composed of layers of structure consisting of a floating gate and a control gate separated by a first insulating film; and, at least, ... | 03/18/2003 |
| 6501147 | Process for manufacturing electronic devices comprising high voltage MOS transistors, and electronic device thus obtained A process for manufacturing an electronic device having an HV MOS transistor with a low multiplication coefficient and a high threshold in a non-implanted area of the substrate, this area having the same conductivity type and the same doping level as the ... | 12/31/2002 |
| 6472701 | Non-volatile semiconductor memory device and its manufacturing method In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a fi... | 10/29/2002 |
| 6420769 | Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions A manufacturing method having the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the L... | 07/16/2002 |
| 6396101 | Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions A method for manufacturing electronic devices, such as memory cells and LV transistors, with salicided junctions, that includes: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining floating gate regions on first areas... | 05/28/2002 |
| 6372577 | Core cell structure and corresponding process for NAND type performance flash memory device A method of forming a NAND-type flash memory device (200 ) includes forming a stacked gate flash memory structure (346) for one or more flash memory cells in a core region (305) and forming a transistor structure having a first gate oxide (336) and a gate... | 04/16/2002 |
| 6350652 | Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions A manufacturing process including: forming a first insulating region on top of an active area; forming a tunnel region at the side of the first insulating region; depositing and defining a semiconductor material layer using a floating gate mask to form a ... | 02/26/2002 |
| 6351008 | Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions The manufacturing method comprises, in sequence, the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions... | 02/26/2002 |
| 6340828 | Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions A manufacturing process including forming a first insulating region on top of an active area; forming a tunnel region laterally to the first insulating region; forming a floating gate region; sealing the floating gate region with an insulating region; for... | 01/22/2002 |
| 6294427 | Non-volatile semiconductor memory device and fabrication method thereof A non-volatile semiconductor memory device is provided with a circuit that protects a tunnel oxide film from the charging phenomenon. This circuit comprises a first junction diode including an N+ -type diffusion layer and a P-type well, and a s... | 09/25/2001 |
| 6291853 | Nonvolatile semiconductor device having a memory cells each of which is constituted of a memory transistor and a selection transistor A tunnel oxide film 120, a first polysilicon layer 164, a poly-poly insulating film 132 and a second polysilicon layer 166 are formed on a semiconductor substrate in a memory cell area. After that, with two photo resists 168-S and 168-M as a mask, pattern... | 09/18/2001 |
| 6287907 | Method of manufacturing a flash memory having a select transistor According to the present invention, there is disclosed a 2-transistors type flash memory, wherein a memory-transistor is composed of layers of structure consisting of a floating gate and a control gate separated by a first insulating film; and, at least, ... | 09/11/2001 |
| 6284602 | Process to reduce post cycling program VT dispersion for NAND flash memory devices In one embodiment, the present invention relates to a method of forming a NAND type flash memory device involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a selec... | 09/04/2001 |
| 6281077 | Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions A method for manufacturing electronic devices, such as memory cells and LV transistors, with salicided junctions, that includes: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining floating gate regions on first areas... | 08/28/2001 |
| 6274411 | Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks A method of forming source and drain regions for LV transistors that includes the steps of forming sacrificial spacers laterally to LV gate regions; forming LV source and drain regions in a self-aligned manner with the sacrificial spacers; removing the sa... | 08/14/2001 |
| 6265739 | Non-volatile semiconductor memory device and its manufacturing method In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a fi... | 07/24/2001 |
| 6251728 | Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions A manufacturing method having the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the L... | 06/26/2001 |
| 6221717 | EEPROM memory cell comprising a selection transistor with threshold voltage adjusted by implantation, and related manufacturing process Process for manufacturing of an integrated structure including at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, including at least a first stage of growth and definition of a gate oxide... | 04/24/2001 |
