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| Number | Title | Issue Date |
| 7439587 | Semiconductor device and method of manufacturing the same An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21),... | 10/21/2008 |
| 7419876 | Method for manufacturing non-volatile memory devices integrated in a semiconductor substrate A method manufactures non-volatile memory devices integrated on a semiconductor substrate and including a matrix of non-volatile memory cells and associated circuitry. The manufacturing method includes: forming a plurality of electrodes of the matrix memory cells, e... | 09/02/2008 |
| 7402495 | Method for manufacturing a semiconductor device A method of manufacturing a semiconductor device includes forming a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type in a predetermined region of the semiconductor substrate of a first conductive typ... | 07/22/2008 |
| 7399662 | Method of manufacturing a thin film transistor device A method of making a thin film transistor device, including forming and patterning a semiconductor film to form first and second semiconductor films in, respectively, low-voltage driven and high-voltage driven thin film transistor formation regions. The method also ... | 07/15/2008 |
| 7371631 | Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-... | 05/13/2008 |
| 7364969 | Semiconductor fabrication process for integrating formation of embedded nonvolatile storage device with formation of multiple transistor device types A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying... | 04/29/2008 |
| 7333366 | Common wordline flash array architecture The memory area on a die required for row (X) and column (Y) decoders is reduced by a plurality of memory array blocks sharing wordlines to a single row decoder. During erase operations, the p-well of unselected memory array blocks is pulled negative to substantiall... | 02/19/2008 |
| 7312503 | Semiconductor memory device including MOS transistors each having a floating gate and a control gate A semiconductor memory device includes a plurality of memory cells, a plurality of local bit lines, a global bit line, a first switch element, and a holding circuit. The memory cell includes first and second MOS transistors. The first MOS transistor has a charge acc... | 12/25/2007 |
| 7297598 | Process for erase improvement in a non-volatile memory device A method of making embedded non-volatile memory devices includes forming a first mask layer overlying a polycrystalline silicon layer in a cell region and a peripheral region on a semiconductor substrate wherein the first mask layer has a plurality of openings in th... | 11/20/2007 |
| 7294883 | Nonvolatile memory cells with buried channel transistors In a nonvolatile memory cell (110), the select gate transistor is formed as a buried channel transistor to increase the transistor current. ... | 11/13/2007 |
| 7230294 | Non-volatile memory devices having a multi-layered charge storage layer and methods of forming the same A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-laye... | 06/12/2007 |
| 7220642 | Protection of active layers of memory cells during processing of other elements A method of fabricating an electronic structure by providing a conductive layer, providing a dielectric layer over the conductive layer, providing first and second openings through the dielectric layer, providing first and second conductive bodies in the first and s... | 05/22/2007 |
| 7193272 | Semiconductor device and method of manufacturing the same An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21),... | 03/20/2007 |
| 7148103 | Multilevel poly-Si tiling for semiconductor circuit manufacture Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by: manufacturing the first electro... | 12/12/2006 |
| 7132330 | Nonvolatile semiconductor memory device with improved gate oxide film arrangement In a nonvolatile semiconductor memory device, an interpoly dielectric film composed of a nitrogen-introduced CVD SiO2 film is used as the gate oxide films of MOS transistors in a low voltage region of a peripheral circuit region. Gate oxide films of MOS t... | 11/07/2006 |
| 7091089 | Method of forming a nanocluster charge storage device In one embodiment, a method of forming a nanocluster charge storage device is provided. A first region of a semiconductor device is identified for locating one or more non-charge storage devices. A second region of the semiconductor device is identified for locating... | 08/15/2006 |
| 6815762 | Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit lines In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conduc... | 11/09/2004 |
| 6703670 | Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention ... | 03/09/2004 |
| 6700143 | Dummy structures that protect circuit elements during polishing Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.... | 03/02/2004 |
| 6690603 | Microcomputer including a flash memory that is two-way programmable A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective... | 02/10/2004 |
| 6680230 | Semiconductor device and method of fabricating the same A method of fabricating a semiconductor device which has a cell array with non-volatile memory transistors and a peripheral circuit including a first transistor and a second transistor as driven by a lower voltage than the first transistor is disclosed. T... | 01/20/2004 |
| 6670234 | Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof A method for fabricating DRAM and flash memory cells on a single chip includes providing a silicon substrate, forming a trench capacitor for each of the DRAM cells in the silicon substrate, forming isolation regions in the silicon substrate which are elec... | 12/30/2003 |
| 6667511 | NAND type core cell structure for a high density flash memory device having a unique select gate transistor configuration A method of forming a NAND-type flash memory device including forming a stacked gate flash memory structure (346) containing an interpoly dielectric layer (322) for one or more flash memory cells in a core region (305). The method also includes forming a ... | 12/23/2003 |
| 6656781 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, HAVING FIRST AND SECOND SEMICONDUCTOR REGIONS WITH FIELD SHIELD ISOLATION STRUCTURES AND A FIELD OXIDE FILM COVERING A JUNCTION BETWEEN SEMICONDUCTOR REGIONS A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover th... | 12/02/2003 |
| 6657249 | Nonvolatile semiconductor memory device with peripheral circuit part comprising at least one of two transistors having lower conductive layer same perpendicular structure as a floating gate A nonvolatile semiconductor memory device capable of readily distinctively forming transistors in a peripheral circuit part and a transistor in a memory cell part while minimizing the number of times of high-temperature heat treatment are obtained. In the... | 12/02/2003 |
| 6646303 | Nonvolatile semiconductor memory device and a method of manufacturing the same The present invention aims to provide high integration of a nonvolatile semiconductor memory device having lots of flash memory cells without causing a reduction in its operating speed. A width taken along a gate-width direction, of a lower conductor film... | 11/11/2003 |
| 6643186 | Nonvolatile memory structures and fabrication methods In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line... | 11/04/2003 |
| 6639269 | Electrically programmable memory cell configuration and method for fabricating it A memory cell contains a planar transistor whose channel region is disposed at a bottom of a depression in a substrate. A floating gate electrode of the transistor adjoins the bottom of the depression, the bottom being provided with a first dielectric dis... | 10/28/2003 |
| 6624015 | Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions The manufacturing method comprises, in sequence, the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions... | 09/23/2003 |
| 6624468 | Semiconductor device including insulated gate field effect transistors In a semiconductor device in which a non-volatile memory element and a p-channel IGFET are mounted on a single substrate, a nitride atom density of a tunnel insulating film of the non-volatile memory element is set to be higher than a nitride atom density... | 09/23/2003 |
| 6617632 | Semiconductor device and a method of manufacturing the same A parallel connection-type nonvolatile memory semiconductor device comprises a plurality of memory cells disposed on a semiconductor substrate in matrix form, each including a gate insulating film, a floating gate electrode, an interlayer film and a contr... | 09/09/2003 |
| 6617636 | Nonvolatile memory structures and fabrication methods In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line... | 09/09/2003 |
| 6614684 | Semiconductor integrated circuit and nonvolatile memory element An information retention capability based on a memory cell which includes pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (... | 09/02/2003 |
| 6608345 | Nonvolatile semiconductor memory device and semiconductor integrated circuit All source regions belonging to a row are electrically connected to one another through a silicon layer (4) in a portion between a bottom surface of a partial-isolation insulating film (5) and an upper surface of a BOX layer (3). These constitute source l... | 08/19/2003 |
| 6605506 | Method of fabricating a scalable stacked-gate flash memory device and its high-density memory arrays A scalable stacked-gate flash memory device and its high-density memory arrays are disclosed by this invention. There are four different spacer techniques used to fabricate a scalable stacked-gate flash memory device: the first spacer technique is used to... | 08/12/2003 |
| 6593158 | Semiconductor memory and manufacturing method of the same A semiconductor memory comprises a first cell (memory cell) including a charge storage layer, and a second cell including a charge storage layer and used with its set threshold value fixed. The threshold value of the second cell is generally apt to return... | 07/15/2003 |
| 6573130 | Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors A process that provides for the manufacture of LV transistors with salicidated junctions on first areas of a substrate, HV transistors on second areas, and memory cells on third areas. The process includes forming LV oxide regions and LV gate regions on t... | 06/03/2003 |
| 6559055 | Dummy structures that protect circuit elements during polishing Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.... | 05/06/2003 |
| 6534363 | High voltage oxidation method for highly reliable flash memory devices A method for forming a high voltage gate oxide having a high quality and reliability for use with non-volatile memory devices is provided. Field oxide isolation regions are formed in the top surface of a semiconductor substrate so as to define a first act... | 03/18/2003 |
| 6531366 | Method and structure for high-voltage device with self-aligned graded junctions A method of fabricating a semiconductor device (300) is disclosed. A low energy ion implantation (318) may form low voltage source and drain regions in a low voltage region (402-3) of a substrate. A low energy implant may also form a portion of source and... | 03/11/2003 |
