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| Number | Title | Issue Date |
| 7439134 | Method for process integration of non-volatile memory cell transistors with transistors of another type A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method inc... | 10/21/2008 |
| 7364951 | Nonvolatile semiconductor memory device and method for manufacturing the same A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit port... | 04/29/2008 |
| 7229876 | Method of fabricating memory A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gate... | 06/12/2007 |
| 7166510 | Method for manufacturing flash memory device A method for manufacturing a flash memory device including the steps of forming a gate oxide film for high voltage on the whole surface of a semiconductor substrate on which a cell region, a low voltage region and a high voltage region have been formed, etching the ... | 01/23/2007 |
| 7148103 | Multilevel poly-Si tiling for semiconductor circuit manufacture Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by: manufacturing the first electro... | 12/12/2006 |
| 6696340 | Semiconductor devices having a non-volatile memory transistor and methods for manufacturing the same A method for manufacturing a semiconductor device having a non-volatile memory transistor may include the steps of forming a floating gate 22 over a semiconductor layer 10 through a first insulation layer 20, forming a second insulation layer 26 that cont... | 02/24/2004 |
| 6661052 | Semiconductor device and method of manufacturing the same A semiconductor device is disclosed, which comprises trench type device isolation regions formed in a semiconductor substrate, semiconductor active regions electrically isolated by the isolation regions, a first electrode layer formed to self-align to the... | 12/09/2003 |
| 6645814 | Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array Thermal oxidation of a peripheral area of a semiconductor substrate is globally restricted with an overlying oxidation resistant layer that is not globally received within the array during formation of a sacrificial oxide layer prior to forming any transi... | 11/11/2003 |
| 6632715 | Semiconductor device having nonvolatile memory cell and field effect transistor A semiconductor device in which a nonvolatile memory cell with a floating gate electrode and a field effect transistor are formed on a semiconductor substrate includes a first conductive layer, a first interlevel insulating film, a second conductive layer... | 10/14/2003 |
| 6630392 | Method for fabricating flash memory device A method for fabricating a flash memory device begins with forming in sequence a tunnel oxide layer, a floating gate, an oxide-nitride-oxide (ONO) layer, a control gate, and a hard mask nitride layer on a silicon substrate. The hard mask nitride layer, th... | 10/07/2003 |
| 6620690 | Method of fabricating flash memory device using self-aligned non-exposure pattern formation process A method of fabricating a flash memory device uses a self-aligned non-exposure pattern formation process. A conductive layer and an oxidation-blocking layer are formed on a stepped pattern including a floating gate pattern and an inter-gate insulating lay... | 09/16/2003 |
| 6611459 | Non-volatile semiconductor memory device A non-volatile semiconductor memory device usable in relatively wide applications and a method of manufacturing the same are provided. A NOR-type flash memory region (2) including a NOR-type memory cell transistor and a DINOR-type flash memory region (3) ... | 08/26/2003 |
| 6593189 | Semiconductor memory reducing current consumption and narrow channel effect and method of manufacturing the same Gate structures, comprising a first insulation film, a first gate material and a gate oxide film, are formed. A second insulation film is formed on side surfaces of the gate structures in the peripheral region. Trenches are formed at a surface of the semi... | 07/15/2003 |
| 6589841 | Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate An improved flash memory device having core stacks and periphery stacks which are protected by first and second thin side walls, side spacers over the side walls, and an HTO layer over the stacks, and side spacer. The flash memory device has an intermetal... | 07/08/2003 |
| 6570216 | EEPROM having a peripheral integrated transistor with thick oxide A process for manufacturing an integrated circuit provides for the formation of a matrix of floating-gate non-volatile memory cells having dual polysilicon levels, with the two polysilicon levels being isolated by a gate dielectric layer (4) and an interp... | 05/27/2003 |
| 6559009 | Method of fabricating a high-coupling ratio flash memory The present invention provides a method of fabricating a flash memory. The method first involves forming a gate oxide layer on a silicon substrate of a semiconductor wafer. Then, a first polysilicon layer, and a silicon nitride layer are formed, respectiv... | 05/06/2003 |
| 6555865 | Nonvolatile semiconductor memory device with a multi-layer sidewall spacer structure and method for manufacturing the same The present invention provides a nonvolatile memory device having high reliability with novel sidewall spacer structures. The gate stack structure for use in a nonvolatile memory device comprises a semiconductor substrate, a gate stack formed on the semic... | 04/29/2003 |
| 6548334 | Capping layer A method of fabricating an improved flash memory device having core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insula... | 04/15/2003 |
| 6534355 | Method of manufacturing a flash memory having a select transistor According to the present invention, there is disclosed a 2-transistors type flash memory, wherein a memory-transistor is composed of layers of structure consisting of a floating gate and a control gate separated by a first insulating film; and, at least, ... | 03/18/2003 |
| 6525370 | Semiconductor device including transistor with composite gate structure and transistor with single gate structure and method for manufacturing the same A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having... | 02/25/2003 |
| 6492672 | Semiconductor device A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of... | 12/10/2002 |
| 6465835 | Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate An improved flash memory device having core stacks and periphery stacks which are protected by first and second thin side walls, side spacers over the side walls, and an HTO layer over the stacks, and side spacer. The flash memory device has an intermetal... | 10/15/2002 |
| 6448608 | Capping layer An improved flash memory device, which comprises core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, th... | 09/10/2002 |
| 6436754 | Selective salicide process by reformation of silicon nitride sidewall spacers A new method of forming selective salicide structures is described whereby robust salicide structures are formed on exposed logic FET's, while blocking salicide formation on memory FET's. Thus, yielding logic FET's with robust salicide structures which ex... | 08/20/2002 |
| 6429480 | Semiconductor device having nonvolatile memory cell and field effect transistor A semiconductor device in which a nonvolatile memory cell with a floating gate electrode and a field effect transistor are formed on a semiconductor substrate includes a first conductive layer, a first interlevel insulating film, a second conductive layer... | 08/06/2002 |
| 6417086 | Method of manufacturing semiconductor device having nonvolatile memory and logic circuit using multi-layered, inorganic mask An inorganic film with a double-layers structure is used as an etching mask in an EEPROM area to pattern a double-layers gate, while a thin inorganic film obtained by removing one layer of the double-layers inorganic film by etching is used as an etching ... | 07/09/2002 |
| 6413840 | Method of gettering layer for improving chemical-mechanical polishing process in flash memory production and semiconductor structure thereof A method of gettering layer for improving chemical mechanical polishing process in flash-memory production is provided to protect a memory element against baking and keep its reliability by blockading mobile electrons with the gettering layer. Moreover, b... | 07/02/2002 |
| 6376310 | Fabrication method of nonvolatile memory device The method of fabricating a nonvolatile memory device having improved reliability and characteristics includes the step of forming a second conductivity type transistor in a peri (peripheral) region of a first conductivity type semiconductor substrate. Th... | 04/23/2002 |
| 6353243 | Process for manufacturing an integrated circuit comprising an array of memory cells A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer (6) an active area for the memory cells; b) forming over said active area for the memory ... | 03/05/2002 |
| 6348378 | Method of making a non-volatile semiconductor device with reduced program disturbance A non-volatile semiconductor device and a method of making such a device having a memory cell formation part and a peripheral circuit part having high and low-voltage transistor formation parts, wherein the device includes an anti-punch through region sur... | 02/19/2002 |
| 6297094 | Semiconductor device with salicide structure and fabrication method thereof A semiconductor device is provided, which makes it possible to decrease the electric sheet resistance of source/drain regions of MOSFETs in a peripheral circuitry without degradation of the data writing speed in nonvolatile memory cells. This device is co... | 10/02/2001 |
| 6287907 | Method of manufacturing a flash memory having a select transistor According to the present invention, there is disclosed a 2-transistors type flash memory, wherein a memory-transistor is composed of layers of structure consisting of a floating gate and a control gate separated by a first insulating film; and, at least, ... | 09/11/2001 |
| 6258648 | Selective salicide process by reformation of silicon nitride sidewall spacers A new method of forming selective salicide structures is described whereby robust salicide structures are formed on exposed logic FET's, while blocking salicide formation on memory FET's. Thus, yielding logic FET's with robust salicide structures which ex... | 07/10/2001 |
| 6255163 | Process for manufacturing selection transistors for nonvolatile serial-flash, EPROM, EEPROM and flash-EEPROM memories in standard or AMG configuration The driving capability of a selection transistor is increased by an N-type implant at the source and drain regions of the selection transistor itself. This implant is conveniently made at the end of the self-aligned etching, using the same self-aligned et... | 07/03/2001 |
| 6248629 | Process for fabricating a flash memory device A method for manufacturing a non-volatile memory device, the device having a core memory cell region and a periphery region, comprising the steps of: forming memory cell gate structures in the core memory cell region; forming active regions adjacent to th... | 06/19/2001 |
| 6245613 | Field effect transistor having a floating gate A field effect transistor which comprises a semiconductor substrate having a source region and a drain region separated by a channel region; a conductive floating gate formed over a first portion of the channel region adjacent to the doped source region a... | 06/12/2001 |
| 6235587 | Method of manufacturing a semiconductor device with reduced arc loss in peripheral circuitry region Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by reducing ARC loss during photoresist stripping associated with plural mask formation in the core memory cell region d... | 05/22/2001 |
| 6228714 | Method for manufacturing nonvolatile memory device A method for manufacturing a nonvolatile memory device is provided. A first conductive layer is formed on a semiconductor substrate. The first conductive layer is patterned such that an isolated resistor pattern is formed on a predetermined region of a pe... | 05/08/2001 |
| 6221717 | EEPROM memory cell comprising a selection transistor with threshold voltage adjusted by implantation, and related manufacturing process Process for manufacturing of an integrated structure including at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, including at least a first stage of growth and definition of a gate oxide... | 04/24/2001 |
| 6211548 | Metal-gate non-volatile memory cell In producing a metal-gate non-volatile memory cell, a layer of oxide is formed over a silicon substrate. A floating gate is then formed over the oxide. Source and drain regions are then formed in the silicon substrate such that at least one of the edges o... | 04/03/2001 |
