Class 257/E21.687 - Floating gate layer used for peripheral FET (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.684. This subclass
No. of patents: 31
Last issue date: 10/21/2008

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Number	Title	Issue Date
7439134	Method for process integration of non-volatile memory cell transistors with transistors of another type A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method inc...	10/21/2008
7371640	Semiconductor device with floating trap type nonvolatile memory cell and method for manufacturing the same The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a seco...	05/13/2008
7223657	Methods of fabricating flash memory devices with floating gates that have reduced seams Methods of fabricating a floating gate of a flash memory cell are provided in which a first polysilicon layer is formed between first and second isolation layers. An upper region of the first polysilicon layer is then oxidized. The oxidized upper region of the first...	05/29/2007
6642105	Semiconductor device having multi-gate insulating layers and methods of fabricating the same A semiconductor device having multi-gate insulating layers and methods of fabricating the same are provided. The semiconductor device includes an isolation region disposed at a predetermined region of a semiconductor substrate. The isolation region define...	11/04/2003
6627928	Method of manufacturing an integrated circuit, for integrating an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the sem...	09/30/2003
6586804	Shallow trench isolation type semiconductor device and method of manufacturing the same A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating ...	07/01/2003
6525370	Semiconductor device including transistor with composite gate structure and transistor with single gate structure and method for manufacturing the same A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having...	02/25/2003
6482698	Method of manufacturing an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the sem...	11/19/2002
6333548	Semiconductor device with etch stopping film There are provided a semiconductor device and a method for manufacturing the same in which a thin film polysilicon film having a small parasitic capacitance which is required for attaining the high-speed operation and high reliability can be used as a res...	12/25/2001
6259133	Method for forming an integrated circuit memory cell and product thereof A method for fabricating an integrated circuit is presented. In the method, a dielectric layer is formed, and then a conductive layer is formed upon the dielectric layer. A base gate may then be patterned from the conductive layer. An intergate dielectric...	07/10/2001
6200857	Method of manufacturing a semiconductor device without arc loss in peripheral circuit region Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by avoiding ARC loss during photoresist stripping associated with plural maskings in the core memory cell region during ...	03/13/2001
6194269	Method to improve cell performance in split gate flash EEPROM Methods to improve cell performance in ROM semiconductor integrated circuit devices, in particular split gate cell flash EEPROM devices, without the need for increasing cell size or for decreasing tunnel oxide thickness. The threshold voltage under a firs...	02/27/2001
6110782	Method to combine high voltage device and salicide process A method for integrating salicide and high voltage device processes in the fabrication of high and low voltage devices on a single wafer is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating a low vol...	08/29/2000
6074914	Integration method for sidewall split gate flash transistor A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a floating gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe ...	06/13/2000
6063663	Method for manufacturing a native MOS P-channel transistor with a process for manufacturing non-volatile memories A method is provided of manufacturing a P-channel native MOS transistor in a circuit integrated on a semiconductor which also includes a matrix of non-volatile memory cells of the floating gate type with two polysilicon levels having an interpoly dielectr...	05/16/2000
6020229	Semiconductor device method for manufacturing There are provided a semiconductor device and a method for manufacturing the same in which a thin film polysilicon film having a small parasitic capacitance which is required for attaining the high-speed operation and high reliability can be used as a res...	02/01/2000
6011293	Semiconductor device having a structure for detecting a boosted potential A p-type well and an n-type well surrounding the p-type well are formed in a p-type semiconductor substrate under a field insulating film. A polysilicon resistance film is formed on the field insulating film simultaneously with a floating gate formed in a...	01/04/2000
5989959	Method of manufacturing nonvolatile semiconductor memory devices with a reduced number of gate electrode forming steps A silicon nitride film and a silicon oxide film are deposited in that order on a WSi film. In a single session of lithography, the gate electrode of a memory cell and the gate electrode of a transistor constituting a peripheral circuit are formed. The sil...	11/23/1999
5976934	Method of manufacturing a nonvolatile semiconductor memory device with select gate bird's beaks In a method of manufacturing a nonvolatile semiconductor memory device, a first polysilicon conductive layer, which is formed in a peripheral circuit region on a semiconductor substrate with a third gate insulating film interposed therebetween, is pattern...	11/02/1999
5925907	Semiconductor device including transistor with composite gate structure and transistor with single gate structure A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having...	07/20/1999
5773861	Single transistor E² PROM memory device A semiconductor memory cell device exhibiting superior cell reliability comprising a dual layer floating gate wherein the thin upper layer of the floating gate overlaps the edges of surrounding field insulating regions and has rounded edges to minimize le...	06/30/1998
5716863	Method of manufacturing semiconductor device having elements different in gate oxide thickness and resistive elements A plurality of device isolation insulating layers are formed on the surface of a semiconductor substrate. A gate insulating layer is formed on the substrate surface between each device isolation insulating layer. After that, a first polysilicon layer is d...	02/10/1998
5686749	Non-volatile semiconductor memory device with thin film transistor formed on a separation insulating film adjacent to a memory cell, and method of making thereof In a non-volatile semiconductor memory device, predetermined number of memory cells each comprising a non-volatile semiconductor memory element of a floating gate type transistor are connected to a first bit line in parallel, and the first bit line is con...	11/11/1997
5677871	Circuit structure for a memory matrix and corresponding manufacturing method A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells including plural rows and columns, with each row being provided with a word line and a control gate line and each column having a bit line; the bit ...	10/14/1997
5635416	Manufacturing method to fabricate a semiconductor integrated circuit with on-chip non-volatile memories A semiconductor memory cell device exhibiting superior cell reliability comprising a dual layer floating gate wherein the thin upper layer of the floating gate overlaps the edges of surrounding field insulating regions and has rounded edges to minimize le...	06/03/1997
5597750	Method of manufacturing a matrix of memory cells having control gates A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells including plural rows and columns, with each row being provided with a word line and a control gate line and each column having a bit line; the bit ...	01/28/1997
5472892	Method of making a non-volatile floating gate memory device with peripheral transistor The present invention discloses a non-volatile memory device having a multi-level gate structure. The storage cell transistor in the cell array region and the transistor in the peripheral circuit region have the same multi-level gate structure. Also, mult...	12/05/1995
5466622	Process for fabricating integrated devices including nonvolatile memories and transistors with tunnel oxide protection A process for simultaneously fabricating memory cells, transistors, and diodes for protecting the tunnel oxide layer of the cells, using the DPCC process wherein the first polysilicon layer is not removed from the transistor area, and the gate regions of ...	11/14/1995
5200636	Semiconductor device having E² PROM and EPROM in one chip An E2 PROM and an EPROM are formed on the same substrate. An E2 PROM memory cell has a floating gate and a control gate. A tunnel insulating film is formed between the floating gate and source/drain regions, thereby constituting a me...	04/06/1993
4697330	Floating gate memory process with improved dielectric The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitan...	10/06/1987
4613956	Floating gate memory with improved dielectric The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitan...	09/23/1986

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Class 257/E21.687 - Floating gate layer used for peripheral FET (EPO)