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| Number | Title | Issue Date |
| 7371640 | Semiconductor device with floating trap type nonvolatile memory cell and method for manufacturing the same The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a seco... | 05/13/2008 |
| 6548855 | Non-volatile memory dielectric as charge pump dielectric A non-volatile memory device for retention of data when electrical power is terminated. The non-volatile memory device includes at least one memory cell and a charge pump for stepping up the incoming voltage supply. The charge pump includes at least one c... | 04/15/2003 |
| 6509225 | Semiconductor device and method of manufacturing the same A semiconductor device comprises a first MOSFET and a second MOSFET. The first MOSFET includes a first gate insulating film formed on a semiconductor substrate and having a relatively large thickness and a first gate electrode composed of a polysilicon fi... | 01/21/2003 |
| 6479346 | Semiconductor memory device and fabrication method thereof In a semiconductor memory device including memory cells and a peripheral circuit unit, a memory cell has a first gate structure formed on a semiconductor substrate; a first impurity region of a first conductive type formed in the substrate on a first side... | 11/12/2002 |
| 6462386 | Semiconductor device and method of manufacturing the same A semiconductor device comprises a first MOSFET and a second MOSFET. The first MOSFET includes a first gate insulating film formed on a semiconductor substrate and having a relatively large thickness and a first gate electrode composed of a polysilicon fi... | 10/08/2002 |
| 6399442 | Method of manufacturing an integrated semiconductor device having a nonvolatile floating gate memory, and related integrated device A method of manufacturing an integrated semiconductor device having at least one non-volatile floating gate memory cell and at least one logic transistor. The method includes growing a first gate oxide layer over a silicon substrate, depositing a first po... | 06/04/2002 |
| 6333223 | Semiconductor device and method of manufacturing the same A semiconductor device comprises a first MOSFET and a second MOSFET. The first MOSFET includes a first gate insulating film formed on a semiconductor substrate and having a relatively large thickness and a first gate electrode composed of a polysilicon fi... | 12/25/2001 |
| 6319780 | Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage Active areas and body regions are formed in a substrate for forming low voltage MOS transistors, high voltage MOS transistors, and EPROM cells. A thermal oxide layer is formed on the substrate, and a first polycrystalline silicon layer is formed on the th... | 11/20/2001 |
| 6251729 | Method of manufacturing a nonvolatile memory In a method of manufacturing a semiconductor device comprising a field-effect transistor and a non-volatile memory element at a surface of a semiconductor body, a first and a second active region of a first conductivity type are defined at the surface of ... | 06/26/2001 |
| 6114203 | Method of manufacturing a MOS integrated circuit having components with different dielectrics The method described provides for the formation of thin thermal oxide on areas of a silicon die intended for memory cells and other components of the peripheral circuits of the memory. To improve the quality of the oxide of the cells essentially in terms ... | 09/05/2000 |
| 6034416 | Semiconductor device and method for fabricating the same The top surface of a substrate in a peripheral circuit region is at a level that is higher than the top surface of the substrate in a memory cell region and that is substantially equal to the top surface of a floating gate electrode. A control gate electr... | 03/07/2000 |
| 6015732 | Dual gate oxide process with increased reliability Within a dual gate oxide process, gate oxide is formed within regions on a substrate. Gate material, such as polysilicon, is placed over a first region. The gate material extends over field oxide surrounding the first region. Gate oxide within a second re... | 01/18/2000 |
| 6004829 | Method of increasing end point detection capability of reactive ion etching by adding pad area A method of forming a semiconductor device includes forming of layers of polysilicon and dielectric layers in manufacturing a semiconductor device and patterning the layers into devices using phototlithography and etching process steps. End point mode det... | 12/21/1999 |
| 5925908 | Integrated circuit including a non-volatile memory device and a semiconductor device An integrated circuit (10) is formed on a semiconductor substrate (20) and includes a non-volatile memory device (12) and a semiconductor device (11). The non-volatile memory device (12) includes a dielectric layer (15) than has a nitrogen composition. Th... | 07/20/1999 |
| 5428572 | Program element for use in redundancy technique for semiconductor memory device Improvement of a fuse for use in the redundancy technique particularly for a semiconductor memory device. The fuse is constituted by an MIS type transistor having a gate insulating layer, which comprises at least two types of insulating films. Redundancy ... | 06/27/1995 |
| 5158902 | Method of manufacturing logic semiconductor device having non-volatile memory The present invention discloses a logic semiconductor device having a non-volatile memory in which a memory cell portion and a logic circuit portion are formed on a single semiconductor substrate, and a floating gate of the memory cell portion and a gate ... | 10/27/1992 |
| 5104819 | Fabrication of interpoly dielctric for EPROM-related technologies A method and a device formed by the method of forming a composite dielectric structure between the floating polysilicon electrode and the control electrode of an EPROM-type device is disclosed. The dielectic is characterized by a thin (0-80 angstroms) the... | 04/14/1992 |
| 5094967 | Method for manufacturing semiconductor device having a non-volatile memory cell and logic regions by using a CVD second insulating film A method for manufacturing a semiconductor substrate device having a non-volatile memory cell region and a logic region including MOS transistors. A first insulating film and a first electrode layer are formed on a semiconductor substrate. Only those port... | 03/10/1992 |
| 5063431 | Semiconductor device having a two-layer gate structure A semiconductor device is disclosed, which comprises source and drain regions formed in a spaced-apart relation to each other on an isolated semiconductor substrate surface, a first conductive layer formed over a channel region between the source and drai... | 11/05/1991 |
| 5034798 | Semiconductor device having a two-layer gate structure A semiconductor device is disclosed, which comprises source and drain regions formed in a spaced-apart relation to each other on an isolated semiconductor substrate surface, a first conductive layer formed over a channel region between the source and drai... | 07/23/1991 |
| 4822750 | MOS floating gate memory cell containing tunneling diffusion region in contact with drain and extending under edges of field oxide A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory dev... | 04/18/1989 |
| 4701776 | MOS floating gate memory cell and process for fabricating same A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory dev... | 10/20/1987 |
| 4377818 | High density electrically programmable ROM An electrically programmable memory array of the floating gate type is made by a process which allows the edges of the floating gates to be aligned with the edges of the control gates which also form address lines. Contacts to individual cells are not nee... | 03/22/1983 |
| 4258466 | High density electrically programmable ROM An electrically programmable memory array of the floating gate type is made by a process which allows the edges of the floating gates to be aligned with the edges of the control gates which also form address lines. Contacts to individual cells are not nee... | 03/31/1981 |
