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| Number | Title | Issue Date |
| 7425482 | Non-volatile memory device and method for fabricating the same A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a plurality of gate structures on a substrate, each gate structure including a first electrode layer for a floating gate; forming a first insulation layer c... | 09/16/2008 |
| 7122430 | Nonvolatile semiconductor memory and manufacturing method for the same The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-elect... | 10/17/2006 |
| 6667507 | Flash memory having memory section and peripheral circuit section A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided o... | 12/23/2003 |
| 6620690 | Method of fabricating flash memory device using self-aligned non-exposure pattern formation process A method of fabricating a flash memory device uses a self-aligned non-exposure pattern formation process. A conductive layer and an oxidation-blocking layer are formed on a stepped pattern including a floating gate pattern and an inter-gate insulating lay... | 09/16/2003 |
| 6603171 | Electronic devices with nonvolatile memory cells of reduced dimensions A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; f... | 08/05/2003 |
| 6596608 | Method of manufacturing non-volatile semiconductor memory device To provide a method for producing a non-volatile semiconductor memory device that can form trenches having different depths in a reduced number of processes. A method for producing a non-volatile semiconductor memory device having a memory cell region and... | 07/22/2003 |
| 6580117 | Non-volatile semiconductor memory device and method of manufacturing the same A non-volatile semiconductor memory device includes a plurality of trenches for element-isolation formed on the main surface of a semiconductor substrate, a nitrided silicon layer formed along the wall surface of the trench, a silicon oxide film for eleme... | 06/17/2003 |
| 6534355 | Method of manufacturing a flash memory having a select transistor According to the present invention, there is disclosed a 2-transistors type flash memory, wherein a memory-transistor is composed of layers of structure consisting of a floating gate and a control gate separated by a first insulating film; and, at least, ... | 03/18/2003 |
| 6518618 | Integrated memory cell and method of fabrication A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunne... | 02/11/2003 |
| 6509222 | Process for manufacturing electronic devices comprising nonvolatile memory cells of reduced dimensions A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; f... | 01/21/2003 |
| 6476438 | Nonvolatile semiconductor memory device and method of manufacturing the same A nonvolatile semiconductor memory device includes a semiconductor substrate having a main surface, a floating gate electrode having a doped polycrystalline silicon film formed on the main surface with a thermal oxide film therebetween, and a doped polycr... | 11/05/2002 |
| 6458655 | Method of manufacturing semiconductor device and flash memory A semiconductor manufacturing method is mainly contemplated, improved to prevent an altered surface layer of a resist from being removed when a single patterned resist is used to provide dry-etch and wet-etch successively. On a semiconductor substrate an ... | 10/01/2002 |
| 6455373 | Semiconductor device having gate edges protected from charge gain/loss A plurality of core gate stacks and periphery gates on the substrate, each core gate stack and periphery gate having at least one side and first and second protective shoulders formed on said plurality of core gate stacks and periphery gates, such that a ... | 09/24/2002 |
| 6436778 | Re-oxidation approach to improve peripheral gate oxide integrity in a tunnel nitride oxidation process A process for fabricating a semiconductor device 20 that includes providing semiconductor substrate 28 having a core region 24 and a peripheral gate region 26. The semiconductor substrate 28 has at least one shallow trench isolation region 30 and at least... | 08/20/2002 |
| 6365457 | Method for manufacturing nonvolatile memory device using self-aligned source process There is provided a method for manufacturing a nonvolatile memory device using a self-aligned source (SAS) process. The method has the steps of forming a field oxide film on a semiconductor substrate, thus defining an active region on the substrate; seque... | 04/02/2002 |
| 6287907 | Method of manufacturing a flash memory having a select transistor According to the present invention, there is disclosed a 2-transistors type flash memory, wherein a memory-transistor is composed of layers of structure consisting of a floating gate and a control gate separated by a first insulating film; and, at least, ... | 09/11/2001 |
| 6248627 | Method for protecting gate edges from charge gain/loss in semiconductor device A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protec... | 06/19/2001 |
| 6235585 | Method for fabricating flash memory device and peripheral area Methods for fabricating a flash memory device which improves both charge retaining characteristics and characteristics of a gate insulating film are disclosed. The methods include the steps of respectively forming a tunneling oxide film and a peripheral o... | 05/22/2001 |
| 6228723 | Method for forming split gate non-volatile memory cells without forming a conductive layer on a boundary region between a memory cell array and peripheral logic A method for forming a split gate non-volatile memory cell in a semiconductor device is described. The semiconductor device is defined by a cell array region, a boundary region, and a peripheral logic region. The method eliminates the formation of a condu... | 05/08/2001 |
| 6214669 | Single-chip contact-less read-only memory (ROM) device and the method for fabricating the device To obtain a small contact-less memory device, a memory device includes a semiconductor chip having a first surface and a second surface located at a level lower than that of the first surface, a memory cell array formed on the second surface, a peripheral... | 04/10/2001 |
| 6207991 | Integrated non-volatile and CMOS memories having substantially the same thickness gates and methods of forming the same A method of forming non-volatile memory (e.g., an EEPROM device) and a CMOS device (e.g., a RAM), on a single die or chip, and a structure formed by the method. In one embodiment, the control gate of the storage transistor as well as the isolation gate of... | 03/27/2001 |
| 6194320 | Method for preparing a semiconductor device In a method for preparing a semiconductor device wherein a first silicon oxide film, a second silicon oxide film and a silicon nitride film are sequentially deposited on a silicon substrate, and both silicon oxide films and the silicon nitride film are pa... | 02/27/2001 |
| 6180457 | Method of manufacturing non-volatile memory device A method of manufacturing a non-volatile memory device is provided. According to an aspect of this method, an isolation layer is formed on a semiconductor substrate including a cell array part and a peripheral circuit part. A floating gate pattern is form... | 01/30/2001 |
| 6177312 | Method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of such device This invention relates to a method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of said device, wherein at least some of the contaminate nitrogen has formed a bond with the surface of ... | 01/23/2001 |
| 6160317 | Method of spacer formation and source protection after self-aligned source formed and a device provided by such a method The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, ... | 12/12/2000 |
| 6159802 | Method of forming a stack-gate of a non-volatile memory on a semiconductor wafer The invention relates to a method of forming a stack-gate of a non-volatile memory. In this method, the stack-gate is formed in a predetermined region of the substrate of a semiconductor wafer. Then, a gate oxide layer, a first gate conductive layer, a di... | 12/12/2000 |
| 6157575 | Nonvolatile memory device and operating method thereof There is provided a nonvolatile memory device and an operating method therof which can perform byte erasing and can be implemented high integration. The nonvolatile memory device has a plurality of cells, each including a stacked gate structure of a float... | 12/05/2000 |
| 6143608 | Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation This invention describes methods for producing gate oxide regions in periphery regions of semiconductor chips, wherein the gate oxide regions have improved electrical properties. The methods involve the deposition of a barrier layer over the periphery of ... | 11/07/2000 |
| 6127696 | High voltage MOS transistor for flash EEPROM applications having a uni-sided lightly doped drain High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide isolation structures are formed as in the prior art. A sacrificial thermal oxide layer simultaneously... | 10/03/2000 |
| 6121670 | Single-chip contact-less read-only memory (ROM) device and the method for fabricating the device To obtain a small contact-less memory device, a memory device includes a semiconductor chip having a first surface and a second surface located at a level lower than that of the first surface, a memory cell array formed on the second surface, a peripheral... | 09/19/2000 |
| 6087221 | Method of fabricating two dissimilar devices with diminished processing steps A method for fabricating dissimilar devices in an integrated circuit. In one embodiment, the method can be used to fabricate flash memory, including MOS transistors and flash cells. The method can be used to substantially cofabricate the MOS transistors a... | 07/11/2000 |
| 6074914 | Integration method for sidewall split gate flash transistor A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a floating gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe ... | 06/13/2000 |
| 6074915 | Method of making embedded flash memory with salicide and sac structure A combined method of fabricating embedded flash memory cells having salicide and self-aligned contact (SAC) structures is disclosed. The SAC structure of the cell region and the salicide contacts of the peripheral region of the semiconductor device are fo... | 06/13/2000 |
| 5989959 | Method of manufacturing nonvolatile semiconductor memory devices with a reduced number of gate electrode forming steps A silicon nitride film and a silicon oxide film are deposited in that order on a WSi film. In a single session of lithography, the gate electrode of a memory cell and the gate electrode of a transistor constituting a peripheral circuit are formed. The sil... | 11/23/1999 |
| 5943262 | Non-volatile memory device and method for operating and fabricating the same A non-volatile memory device includes a plurality of bit lines arranged in parallel at predetermined intervals, a plurality of word lines arranged perpendicularly to the bit lines and at predetermined intervals, a plurality of unit cells having a stacked ... | 08/24/1999 |
| 5933730 | Method of spacer formation and source protection after self-aligned source is formed and a device provided by such a method The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, ... | 08/03/1999 |
| 5912842 | Nonvolatile PMOS two transistor memory cell and array A nonvolatile memory array is disclosed which includes a plurality of PMOS two-transistor (2T) memory cells. Each 2T cell includes a PMOS floating gate transistor and a PMOS select transistor and is connected between a bit line and a common source line. T... | 06/15/1999 |
| 5899713 | Method of making NVRAM cell with planar control gate A nonvolatile memory cell utilizing planar control gates, which provides advantages of being compatible with self-aligned silicide processes and providing a planar surface for subsequent wiring processes. A substrate defines a first NVRAM region having la... | 05/04/1999 |
| 5889305 | Non-volatile semiconductor memory device having storage cell array and peripheral circuit In a non-volatile semiconductor memory device having a storage cell array and a peripheral circuit, the thickness of a gate oxide layer of the peripheral circuit area is independent of the formation of an O--N--O insulation layer on the storage cell area.... | 03/30/1999 |
| 5847427 | Non-volatile semiconductor memory device utilizing an oxidation suppressing substance to prevent the formation of bird's breaks A non-volatile semiconductor memory device is provided that includes a semiconductor substrate having a first conductivity type, and diffusion regions having a second conductivity type formed in the surface of the semiconductor substrate at predetermined ... | 12/08/1998 |
