Did You Know...
...that two musicians were responsible for the invention of color print film? Fascinated by photography, Leopold Godowsky and Leopold Mannes worked together to produce an easy-to-use, practical color film. They worked full time as music teachers and gave concerts while experimenting during their off hours in Mannes' kitchen. Their success earned them full-time, well-paying jobs at Kodak and their efforts resulted in Kodachrome film, which was introduced in 1935.
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| Number | Title | Issue Date |
| 7442606 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device includes providing a semiconductor substrate in which a floating gate pattern is formed. A dielectric layer, a conductive layer for a control gate, a tungsten silicide layer, a first silicon oxynitride layer, a hard m... | 10/28/2008 |
| 7439121 | Dielectric film and method of forming it, semiconductor device, non-volatile semiconductor memory device, and production method for semiconductor device In a film formation method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of the silicon surface in advance, and the film formation method removes the hydrogen by exposing the silic... | 10/21/2008 |
| 7439157 | Isolation trenches for memory devices A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric la... | 10/21/2008 |
| 7435646 | Method for forming floating gates within NVM process A semiconductor process and apparatus includes forming a semiconductor device by depositing a layer of nitride (20) over a semiconductor structure (10), patterning and etching the nitride layer to form a patterned nitride layer (42, 44), deposit... | 10/14/2008 |
| 7429511 | Method of forming a tunneling insulating layer in nonvolatile memory device A method of forming a tunneling insulating layer having a size smaller than the size obtained by the resolution of a photolithography process is provided. The method includes the steps of forming a first insulating layer and a second insulating layer on a substrate,... | 09/30/2008 |
| 7410869 | Method of manufacturing a semiconductor device In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the... | 08/12/2008 |
| 7411244 | Low power electrically alterable nonvolatile memory cells and arrays Nonvolatile memory cells having a conductor-filter system, a conductor-insulator system, and a charge-injection system are provided. The conductor-filter system provides band-pass filtering function, charge-filtering function, and mass-filtering function to charge-c... | 08/12/2008 |
| 7410871 | Split gate type flash memory device and method for manufacturing same A split gate type flash memory device and a method of manufacturing the split gate type flash memory device are disclosed. The split gate type flash memory device includes a silicon epitaxial layer formed in an active region of a bulk silicon substrate and a disturb... | 08/12/2008 |
| 7399672 | Methods of forming nonvolatile memory devices Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semicondu... | 07/15/2008 |
| 7397079 | Non-volatile memory device and methods of forming the same A non-volatile memory device includes a control gate electrode disposed on a substrate with a first insulation layer interposed therebetween and a floating gate disposed in a hole exposing substrate through the control gate electrode and the first insulation layer. ... | 07/08/2008 |
| 7396723 | Method of manufacturing EEPROM device A method of manufacturing an EEPROM device can reduce the cell area. The method of manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) includes forming a mask pattern over a semiconductor substrate; forming a gate oxide layer over a top of ... | 07/08/2008 |
| 7396722 | Memory device with reduced cell area The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk subst... | 07/08/2008 |
| 7393745 | Method for fabricating self-aligned double layered silicon-metal nanocrystal memory element A nanocrystal memory element and a method for fabricating the same are proposed. The fabricating method involves selectively oxidizing polysilicon not disposed beneath and not covered with a plurality of metal nanocrystals, and leaving intact the polysilicon dispose... | 07/01/2008 |
| 7387933 | EEPROM device and method of fabricating the same A memory device comprises a semiconductor substrate of a first conductive type, a memory transistor, a select transistor, a floating junction region, a common source region, and a bit line junction region. The floating junction region is formed of a second conductiv... | 06/17/2008 |
| 7374995 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device including a memory cell and a selection transistor, and the memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposi... | 05/20/2008 |
| 7375393 | Non-volatile memory (NVM) retention improvement utilizing protective electrical shield An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created ... | 05/20/2008 |
| 7374997 | Method of manufacturing flash memory device A method of manufacturing flash memory devices includes depositing a nitride film over a semiconductor substrate and forming an oxide film below the nitride film using an oxidization process involving an anneal process. A tunnel oxide film or an ONO2 oxide film havi... | 05/20/2008 |
| 7371640 | Semiconductor device with floating trap type nonvolatile memory cell and method for manufacturing the same The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a seco... | 05/13/2008 |
| 7372098 | Low power flash memory devices A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and ... | 05/13/2008 |
| 7361553 | Semiconductor device manufacturing method A memory transistor and a high breakdown voltage MOS transistor are easily formed on the same semiconductor substrate without changing the operational characteristics of the memory transistor. The process of forming the tunnel insulation film of the memory transisto... | 04/22/2008 |
| 7358561 | Source lines for NAND memory devices A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first conductive layer formed on a substrate and coupled to source select gates associated with the two or more column... | 04/15/2008 |
| 7351629 | Method of forming non-volatile memory device A non-volatile memory device comprises an active region disposed in a predetermined region of a semiconductor substrate, a selection gate electrode crossing over the active region, and a floating gate electrode disposed on the active region parallel to the selection... | 04/01/2008 |
| 7352035 | Flash memory devices and methods for fabricating flash memory devices A flash memory device includes a cell string having a plurality of cell transistors connected in series, and a string selection transistor and a ground selection transistor connected to both ends of the cell string, respectively, wherein the cell transistor has a ch... | 04/01/2008 |
| 7348237 | NOR flash memory cell with high storage density Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second... | 03/25/2008 |
| 7348241 | Cell structure of EPROM device and method for fabricating the same Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked ... | 03/25/2008 |
| 7348236 | Formation of memory cells and select gates of NAND memory arrays Apparatus and methods are provided. Floating-gate memory cells and select gates of NAND memory arrays are formed concurrently by anisotropically removing portions of a second conductive layer disposed on a first conductive layer such that remaining portions of the s... | 03/25/2008 |
| 7341913 | Method of manufacturing non-volatile memory The invention is directed to a method for manufacturing a non-volatile memory. The method comprises steps of forming a mask layer on a substrate. An isolation structure is formed in the mask layer and the substrate, wherein the top surface of the isolation structure... | 03/11/2008 |
| 7341911 | Method of making EEPROM transistor pairs for block alterable memory A block alterable memory cell has a select control gate extending from a floating gate region to a drain region. The block alterable memory cell comprises a substrate layer that further includes a source implant region, a floating gate transistor region, and a drain... | 03/11/2008 |
| 7338859 | Non-volatile memory cells having floating gate and method of forming the same A non-volatile memory cell having a floating gate and a method of forming the same. The non-volatile memory cell includes a device isolation layer that is formed in a semiconductor substrate and defines an active region. A floating gate is disposed over the active r... | 03/04/2008 |
| 7329577 | Method of manufacturing nonvolatile semiconductor storage device In a method of manufacturing a nonvolatile semiconductor storage device, an element isolation region is formed in a semiconductor substrate, a tunnel oxide film and a polysilicon layer are successively formed on the semiconductor substrate, and nitrogen ions are the... | 02/12/2008 |
| 7323741 | Semiconductor nonvolatile memory device A low cost semiconductor nonvolatile memory device capable of high speed programming, using an inversion layer as the wiring, and a manufacturing method for that device. The semiconductor memory device includes an auxiliary electrode at a position between and in par... | 01/29/2008 |
| 7319058 | Fabrication method of a non-volatile memory A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first ... | 01/15/2008 |
| 7314796 | Methods for reducing wordline sheet resistance The present invention is directed to forming memory wordlines having a relatively lower sheet resistance. In one embodiment, a control-gate poly layer including a first and a second poly-Si portion is deposited. a The first poly-Si portion is deposited on a semicond... | 01/01/2008 |
| 7312490 | Vertical memory device and method Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first... | 12/25/2007 |
| 7306992 | Flash memory device and method of fabricating the same A flash memory device includes control gates that are formed to completely surround the top and sides of floating gates. The control gates are located between the floating gates that are adjacent in the word line direction as well as the floating gates that are adja... | 12/11/2007 |
| 7303957 | Method of fabricating a flash memory device A method of fabricating a flash memory device using a process for forming a self-aligned floating gate is provided. The method comprises forming mask patterns on a substrate, etching the substrate using the mask patterns as an etch mask to form a plurality of trench... | 12/04/2007 |
| 7303958 | Semiconductor device and method of manufacturing the same Disclosed herein is a semiconductor device and method of manufacturing the same. A step between a memory cell formed in a cell region and a transistor formed in a peripheral circuit region is minimized, and the height of a gate in the memory cell is minimized. Accor... | 12/04/2007 |
| 7297634 | Method and apparatus for semiconductor device and semiconductor memory device Method and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for semiconductor device and nonvolatile memory device. The device comprises a strain source, an injection filter, a first conductive region, a second conductive... | 11/20/2007 |
| 7297599 | Method of fabricating semiconductor device A method of fabricating a semiconductor device includes forming on a semiconductor substrate a gate electrode with a gate insulating film being interposed between the substrate and the electrode, forming an insulating film for element isolation protruding from a sur... | 11/20/2007 |
| 7279384 | Semiconductor memory and method for manufacturing the same A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a P type silicon substrate, a control gate CG and a pair of electrically isolated floating gates. Plural projections are formed in the silicon substrate, ... | 10/09/2007 |
