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| Number | Title | Issue Date |
| 7439575 | Protection against in-process charging in silicon-oxide-nitride-oxide-silicon (SONOS) memories A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first ... | 10/21/2008 |
| 7432178 | Bit line implant A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A ... | 10/07/2008 |
| 7413950 | Methods of forming capacitors having storage electrodes including cylindrical conductive patterns A capacitor is provided including a storage node contact pad and a storage electrode. The storage electrode includes at least two cylindrical conductive patterns. The at least two cylindrical conductive patterns are electrically coupled to a portion of a surface of ... | 08/19/2008 |
| 7410845 | Dual-gate device and method A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provide... | 08/12/2008 |
| 7399662 | Method of manufacturing a thin film transistor device A method of making a thin film transistor device, including forming and patterning a semiconductor film to form first and second semiconductor films in, respectively, low-voltage driven and high-voltage driven thin film transistor formation regions. The method also ... | 07/15/2008 |
| 7399675 | Electronic device including an array and process for forming the same An electronic device can include an NVM array, wherein portions of word lines are formed within trenches. Insulating features are formed over heavily doped regions within the substrate. In one embodiment, charge storage stacks and a control gate electrode layer can ... | 07/15/2008 |
| 7394127 | Non-volatile memory device having a charge storage oxide layer and operation thereof A non-volatile memory device includes a pair of source/drain regions disposed in a semiconductor substrate, having a channel region between them. A charge storage oxide layer is disposed on the channel region and overlaps part of each of the pair of source/drain reg... | 07/01/2008 |
| 7391078 | Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace... | 06/24/2008 |
| 7381620 | Oxygen elimination for device processing A method includes forming at least a portion of a semiconductor device in a processing chamber containing oxygen and removing substantially all of the oxygen from the processing chamber. The method further includes forming remaining portions of the semiconductor dev... | 06/03/2008 |
| 7378314 | Source side injection storage device with control gates adjacent to shared source/drain and method therefor A storage device has a two bit cell in which the select electrode is nearest the channel between two storage layers. Individual control electrodes are over individual storage layers. Adjacent cells are separated by a doped region that is shared between the adjacent ... | 05/27/2008 |
| 7371642 | Multi-state NROM device An array of NROM flash memory cells configured to store at least two bits per four F2. Split vertical channels are generated along each side of adjacent pillars. A single control gate is formed over the pillars and in the trench between the pillars. The s... | 05/13/2008 |
| 7368347 | Dual bit flash memory devices and methods for fabricating the same Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided ove... | 05/06/2008 |
| 7361560 | Method of manufacturing a dielectric layer in a memory device that includes nitriding step A method for manufacturing a dielectric layer structure for a non-volatile memory cell is provided. A method includes forming a first dielectric layer for tunneling on a semiconductor substrate, a second dielectric layer on the first dielectric layer to store charge... | 04/22/2008 |
| 7361555 | Trench-gate transistors and their manufacture A trench-gate transistor has an integral first layer of silicon dioxide extending from the upper surface of the semiconductor body over top corners of each cell array trench. The integral first layer also provides a thin gate dielectric insulating layer for a thick ... | 04/22/2008 |
| 7344923 | NROM semiconductor memory device and fabrication method An NROM semiconductor memory device and fabrication method are disclosed. According to one aspect, a method for fabricating an NROM semiconductor memory device can include providing a plurality of u-shaped MOSFETs, which are spaced apart from one another and have a ... | 03/18/2008 |
| 7341914 | Method for forming a non-volatile memory and a peripheral device on a semiconductor substrate A method for forming a semiconductor device includes forming a first gate electrode over a semiconductor substrate, wherein the first gate electrode comprises silicon and forming a second gate electrode over the semiconductor substrate and adjacent the first gate el... | 03/11/2008 |
| 7341918 | Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than tw... | 03/11/2008 |
| 7335939 | Semiconductor memory device and method of production An array of charge-trapping memory cells and pluralities of parallel wordlines and parallel bitlines running transversely to the wordlines are arranged on a substrate surface. Gate electrodes are located between the wordlines and bitlines and are, in their sequence ... | 02/26/2008 |
| 7314798 | Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the tr... | 01/01/2008 |
| 7307027 | Void free interlayer dielectric A method of forming a dielectric between memory cells in a device includes forming multiple memory cells, where a gap is formed between each of the multiple memory cells. The method further includes performing a high density plasma deposition (HDP) process to fill a... | 12/11/2007 |
| 7285463 | Method of fabricating non-volatile memory A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the subs... | 10/23/2007 |
| 7279740 | Band-engineered multi-gated non-volatile memory device with enhanced attributes Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase wi... | 10/09/2007 |
| 7279736 | Nonvolatile memory device and methods of fabricating and driving the same Nonvolatile memory devices and methods of fabricating and driving the same are disclosed. Disclosed devices and method comprises: growing an oxide layer on a substrate and depositing a nitride layer on the oxide layer; patterning the nitride layer; forming injection... | 10/09/2007 |
| 7256444 | Local SONOS-type nonvolatile memory device and method of manufacturing the same Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each... | 08/14/2007 |
| 7244652 | Method of forming a split programming virtual ground SONOS memory A method of forming an SPVG SONOS memory. First, a substrate having a well and a plurality of select gate structures is provided. Then, a plurality of sacrificial spacers are formed alongside each select gate structure, and an implantation process is performed to fo... | 07/17/2007 |
| 7235449 | Method of forming a gate oxide film for a high voltage region of a flash memory device A method of forming a gate oxide film for high voltage region of semiconductor devices includes forming patterns on a semiconductor substrate having a high voltage region, thereby exposing only a gate oxide film formation region for high voltage, forming a metal oxi... | 06/26/2007 |
| 7217972 | Semiconductor device A semiconductor storage device showing a good memory characteristic, and a manufacturing method thereof, includes a semiconductor layer, a stacked body including a first insulating layer, a charge trapping layer, and a second insulating layer that are provided above... | 05/15/2007 |
| 7202150 | Semiconductor memory device and manufacturing method therefor A semiconductor memory device, adapted for storing plural bits per cell to be able to accomplish high storage density by a simplified structure, includes a plurality of first gate electrodes extending parallel to one another along one direction and a plurality of se... | 04/10/2007 |
| 7202523 | NROM flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the ga... | 04/10/2007 |
| 7196008 | Aluminum oxide as liner or cover layer to spacers in memory device For fabricating a memory device, spacers are formed to sides of word-line gates. In addition, aluminum oxide is formed as one of a liner layer or a cover layer to the spacers. The aluminum oxide has a chemical composition of Al2O3 for example. ... | 03/27/2007 |
| 7186616 | Method of removing nanoclusters in a semiconductor device A method for removing nanoclusters from a semiconductor device includes etching a selected portion of an insulating layer, flowing a reducing gas over the semiconductor device at a temperature in a range of 400–900 degrees Celsius, and flowing a gas comprising hal... | 03/06/2007 |
| 7166512 | Method of fabricating non-volatile memory A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the subs... | 01/23/2007 |
| 7157335 | Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally us... | 01/02/2007 |
| 7144777 | Non-volatile memory and manufacturing method thereof A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate struct... | 12/05/2006 |
| 7144829 | Method for fabricating semiconductor device and semiconductor substrate A first thermal treatment, which is performed at a temperature within 650–750° C. for 30–240 minutes, and thereafter a second thermal treatment, which is performed at a temperature within 900–1100° C. for 30–120 minutes, are performed as the initial therma... | 12/05/2006 |
| 7132335 | Semiconductor device with localized charge storage dielectric and method of making same An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage d... | 11/07/2006 |
| 7132336 | Method and apparatus for forming a memory structure having an electron affinity region An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric region formed over a channel region. A doped region is formed between a top portion and a bottom por... | 11/07/2006 |
| 7126172 | Integration of multiple gate dielectrics by surface protection A multiple gate oxidation process is provided. The process comprises the steps of (a) providing a silicon substrate (203) having a sacrificial oxide layer (207) thereon; (b) depositing and patterning a first layer of photoresist (209) on the sac... | 10/24/2006 |
| 7115472 | Process for manufacturing a dual charge storage location memory cell A process for manufacturing a dual charge storage location electrically programmable memory cell that includes the steps of forming a central insulated gate over a semiconductor substrate; forming physically separated charge-confining layers stack portions of a diel... | 10/03/2006 |
| 6967388 | Semiconductor devices and methods for fabricating the same Semiconductor devices and methods for fabricating the same include a device isolation layer formed at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. The device further includes... | 11/22/2005 |
