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...During the Civil War, the Confederacy established its own Patent Office which issued 266 patents, a third of which concerned implements of war.
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| Number | Title | Issue Date |
| 7423283 | Strain-silicon CMOS using etch-stop layer and method of manufacture Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed silicon nitride layer to provide ... | 09/09/2008 |
| 7402496 | Complementary metal-oxide-semiconductor device and fabricating method thereof A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a f... | 07/22/2008 |
| 7400005 | Semiconductor memory device having ferroelectric capacitors with hydrogen barriers A semiconductor memory device, which prevents the penetration of hydrogen or moisture to a ferroelectric capacitor from its surrounding area including a contact plug portion, comprises a ferroelectric capacitor formed above a semiconductor substrate, a first hydroge... | 07/15/2008 |
| 7394090 | Non-volatile memory and the fabrication method A non-volatile memory comprising: a first substrate (100) and a second substrate (110), the first substrate (100) having a plurality of switching elements (4) arranged in matrix, and a plurality of first electrodes (18) connected t... | 07/01/2008 |
| 7390679 | Method for manufacturing ferroelectric memory device A method for manufacturing a ferroelectric capacitor, includes the steps of: forming a ferroelectric capacitor layer having a lower electrode layer, a ferroelectric layer and an upper electrode layer on a base substrate; forming a titanium oxide layer on the ferroel... | 06/24/2008 |
| 7368298 | Method of manufacturing ferroelectric semiconductor device An Ir film, an IrOx film, a Pt film, a PtO film and a Pt film are formed, and thereafter a PLZT film is formed. Then, heat treatment at 600° C. or lower is performed by the RTA method in an atmosphere containing Ar and O2 to thereby crystalliz... | 05/06/2008 |
| 7323349 | Self-aligned cross point resistor memory array A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the... | 01/29/2008 |
| 7309617 | MRAM memory cell with a reference layer and method for fabricating The invention relates to a method for fabricating a reference layer for MRAM memory cells and an MRAM memory cell equipped with a reference layer of this type. A reference layer of this type comprises two magnetically coupled layers having a different Curie temperat... | 12/18/2007 |
| 7297558 | Method of manufacturing semiconductor device A W plug (24) is formed and a W oxidation preventing barrier metal film (25) is formed thereon. After that, an SiON film (27) thinner than the W oxidation preventing barrier metal film (25) is formed and Ar sputter etching is performed on... | 11/20/2007 |
| 7291505 | Method of manufacturing a ferroelectric device The invention relates to a ferroelectric device (10) with a body (11) comprising a substrate (1) and a ferroelectric layer (2) provided with a connection conductor (3) on a side facing away from the substrate (1), which ferr... | 11/06/2007 |
| 7244981 | Scalable high performance non-volatile memory cells using multi-mechanism carrier transport A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate includes a plurality of diffusion regions that are each formed between a pair of planar select gates. In a ... | 07/17/2007 |
| 7217969 | Flip FERAM cell and method to form same A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelect... | 05/15/2007 |
| 7214977 | Ferroelectric thin film, method of manufacturing the same, ferroelectric memory device and ferroelectric piezoelectric device A ferroelectric thin film formed of a highly oriented polycrystal in which 180° domains and 90° domains arrange at a constant angle to an applied electric field direction in a thin film plane and reversely rotate in a predetermined electric field. ... | 05/08/2007 |
| 7186573 | Flip FERAM cell and method to form same A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelect... | 03/06/2007 |
| 7151001 | Fabrication method of self-aligned ferroelectric gate transistor using buffer layer of high etching selectivity A fabrication method of a self-aligned ferroelectric gate transistor using a buffer layer of high etching selectivity is disclosed. A stacked structure is formed with a buffer layer with high etching selectivity inserted between a silicon substrate and a ferroelectr... | 12/19/2006 |
| 7132298 | Fabrication of nano-object array This disclosure relates to a system and method for creating nano-object arrays. A nano-object array can be created by exposing troughs in a corrugated surface to nano-objects and depositing the nano-objects within or orienting the nano-objects with the troughs. ... | 11/07/2006 |
| 7109540 | Semiconductor device for restraining short circuiting and method of manufacturing thereof A method of manufacturing a semiconductor device is provided including: forming a groove in an insulation film; forming a lower electrode material film on the insulation film and in the groove; forming a ferroelectric material film on the lower electrode material fi... | 09/19/2006 |
| 7081380 | Method of forming a conductive pattern of a semiconductor device and method of manufacturing a non-volatile semiconductor memory device using the same A method of forming a conductive pattern of a semiconductor device includes forming a conductive layer is on a substrate, forming a polishing protection layer on the substrate including over the conductive layer, and forming a step compensation layer on the polishin... | 07/25/2006 |
| 7034374 | MRAM layer having domain wall traps A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. ... | 04/25/2006 |
| 7026677 | Magnetoresistive element, magnetic memory cell, and magnetic memory device, and method for manufacturing the same The present invention provides a magnetic memory device capable of performing stable operation efficiently using a magnetic field generated by write current and formed with high precision while realizing a compact configuration. Since a plating film is used for at l... | 04/11/2006 |
| 6649963 | Ferroelectric memory cell for VLSI RAM A method of forming a semiconductor memory device on a silicon substrate includes implanting doping impurities of a first type in the silicon substrate to form a conductive channel of a first type for use as a gate junction region, forming a MOS capacitor... | 11/18/2003 |
| 6623989 | Nonvolatile ferroelectric memory and method for fabricating the same Nonvolatile ferroelectric memory and method for fabricating the same can reduce fatigue caused by repetitive switching, drop an operation voltage, and increase an operation speed of the nonvolatile ferroelectric memory. The nonvolatile ferroelectric memor... | 09/23/2003 |
| 6580633 | Nonvolatile semiconductor memory device A semiconductor memory device comprising: an active layer in which are formed a transistor source, channel and drain; a gate for the transistor; a layer of ferroelectric material; and an electrode for applying a voltage to the ferroelectric material; the ... | 06/17/2003 |
| 6574131 | Depletion mode ferroelectric memory device and method of writing to and reading from the same Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Such memory cells find use in non-volatile memory devices as well as other electronic systems having non-volatile memory storage. Various embodiments are described ... | 06/03/2003 |
| 6570202 | Ferroelectric integrated circuit having low sensitivity to hydrogen exposure and method for fabricating same A hydrogen barrier layer is formed above a ferroelectric thin film in an integrated circuit. The hydrogen barrier layer is directly over a protected segment of the ferroelectric thin film, while a sacrificial segment of the ferroelectric thin film extends... | 05/27/2003 |
| 6509592 | Ferroelectric memory A ferroelectric memory includes a well region, which is defined in a semiconductor substrate and extends in a direction, a bit line also extending in the direction and a source line also extending in the direction. First, second and third memory cells are... | 01/21/2003 |
| 6442059 | Nonvolatile ferroelectric memory and method for fabricating the same Nonvolatile ferroelectric memory and method for fabricating the same can reduce fatigue caused by repetitive switching, drop an operation voltage, and increase an operation speed of the nonvolatile ferroelectric memory. The nonvolatile ferroelectric memor... | 08/27/2002 |
| 6396093 | Ferroelectric memory with reduced capacitance of ferroelectric gate layer On part of a semiconductor layer 1 between a drain region 2 and a source region 3 are formed in succession; a gate oxide film 4, a floating gate electrode 5, a ferroelectric layer 6, and a control gate electrode 7. A silicon oxide film 9 of a dielectric c... | 05/28/2002 |
| 6333528 | Semiconductor device having a capacitor exhibiting improved moisture resistance A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 | 12/25/2001 |
| 6294438 | Semiconductor device having capacitor and manufacturing method thereof A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 | 09/25/2001 |
| 6225156 | Ferroelectric integrated circuit having low sensitivity to hydrogen exposure and method for fabricating same A hydrogen barrier layer is formed above a ferroelectric thin film in an integrated circuit. The hydrogen barrier layer is directly over a protected segment of the ferroelectric thin film, while a sacrificial segment of the ferroelectric thin film extends... | 05/01/2001 |
| 6169304 | Semiconductor device having a passivation layer which minimizes diffusion of hydrogen into a dielectric layer A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 | 01/02/2001 |
| 6165802 | Method of fabricating ferroelectric integrated circuit using oxygen to inhibit and repair hydrogen degradation An integrated circuit is formed that contains a ferroelectric element comprising metal oxide material containing at least two metals. An oxygen-recovery anneal is conducted in ambient oxygen at a temperature range from 300° to 1000° C. for a time period... | 12/26/2000 |
| 6151243 | Ferroelectric memory device having folded bit line architecture A ferroelectric memory device includes a plurality of groups of active areas, each active area having two memory cells, and a plurality of pairs of conductive lines arranged in a parallel fashion, each conductive line having a word line and a plate line, ... | 11/21/2000 |
| 6146904 | Method of making a two transistor ferroelectric memory cell The method of forming the two transistor semi-conductor structure includes forming a device area for a MOS transistor and for a ferroelectric memory (FEM) gate unit on a silicon substrate. A conventional MOS transistor is formed on the substrate. A FEM ce... | 11/14/2000 |
| 6077716 | Matrix type multiple numeration system ferroelectric random access memory using leakage current The present invention relates to a matrix type multiple numeration system ferroelectric random access memory using a leakage current of dielectric, which is non-volatile and with which a multiple numeration system is realized, and a method for manufacturi... | 06/20/2000 |
| 6048738 | Method of making ferroelectric memory cell for VLSI RAM array A method of forming a semiconductor memory device on a silicon substrate includes implanting doping impurities of a first type in the silicon substrate to form a conductive channel of a first type for use as a gate junction region, forming a MOS capacitor... | 04/11/2000 |
| 6022774 | Method for production of semiconductor device A semiconductor device is produced by a method which comprises forming a conductor pattern in or on a semiconductor layer, covering the surface of the conductor pattern with an antioxidant conductor layer, forming a first insulating layer on the semicondu... | 02/08/2000 |
| 6018171 | Shallow junction ferroelectric memory cell having a laterally extending p-n junction and method of making the same A method of forming the FEM cell semi-conductor structure includes forming a device area for the ferroelectric memory (FEM) gate unit on a silicon substrate. Appropriate impurities are implanted into the device area to form conductive channels, for use as... | 01/25/2000 |
| 5986298 | Matrix type multiple numeration system ferroelectric random access memory using leakage current The present invention relates to a matrix type multiple numeration system ferroelectric random access memory using a leakage current of dielectric, which is non-volatile and with which a multiple numeration system is realized, and a method for manufacturi... | 11/16/1999 |
