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| Number | Title | Issue Date |
| 7427536 | High density stepped, non-planar nitride read only memory A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge storage regions in its nitride layer and a pair of source/drain regions that are shared with adjacent cells... | 09/23/2008 |
| 7422932 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device includes a semiconductor substrate, a memory cell region which is disposed on the semiconductor substrate and has a transistor array of a stacked gate structure having a floating gate, a Ti-containing barrier which is dispos... | 09/09/2008 |
| 7419868 | Gated diode nonvolatile memory process A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Various embodiments may include or exclude a diffusion barrier structure between the diode nodes. Example embodiments include the indiv... | 09/02/2008 |
| 7358120 | Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell... | 04/15/2008 |
| 7312490 | Vertical memory device and method Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first... | 12/25/2007 |
| 7279736 | Nonvolatile memory device and methods of fabricating and driving the same Nonvolatile memory devices and methods of fabricating and driving the same are disclosed. Disclosed devices and method comprises: growing an oxide layer on a substrate and depositing a nitride layer on the oxide layer; patterning the nitride layer; forming injection... | 10/09/2007 |
| 7265409 | Non-volatile semiconductor memory A non-volatile semiconductor memory having a memory transistor including a stacked-layer film formed between a semiconductor substrate and a gate electrode and having a charge storage ability, a first conductivity type region of the semiconductor substrate in which ... | 09/04/2007 |
| 7256444 | Local SONOS-type nonvolatile memory device and method of manufacturing the same Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each... | 08/14/2007 |
| 7247539 | Manufacturing method of semiconductor device and semiconductor device A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; patterning the first member to be patterned to form a plurality of parallel linear patterns and a connecting portion wh... | 07/24/2007 |
| 7244981 | Scalable high performance non-volatile memory cells using multi-mechanism carrier transport A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate includes a plurality of diffusion regions that are each formed between a pair of planar select gates. In a ... | 07/17/2007 |
| 7227233 | Silicon-on-insulator (SOI) Read Only Memory (ROM) array and method of making a SOI ROM A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell... | 06/05/2007 |
| 7202523 | NROM flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the ga... | 04/10/2007 |
| 7129135 | Nonvolatile semiconductor memory device and method for fabricating the same A first conductive film for forming a plurality of word lines is formed in a memory cell array formation region of a semiconductor substrate for a nonvolatile semiconductor memory device, and a second conductive film is formed in a semiconductor device formation reg... | 10/31/2006 |
| 7112486 | Method for fabricating semiconductor device by using radical oxidation The present invention provides a method for fabricating a semiconductor device having a dual gate dielectric structure capable of obtaining a simplified process and improving device reliability. The method includes the steps of: forming an insulation layer on a subs... | 09/26/2006 |
| 6664586 | Memory device and manufacturing method thereof The invention provides a memory device including a memory substrate, an insulating layer, a shielding metal layer, a second dielectric layer and a second metal layer. The memory substrate includes a substrate, a memory cell area, a peripheral circuit area... | 12/16/2003 |
| 6642148 | RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The se... | 11/04/2003 |
| 6636433 | Electronic device and recording method using the same An electronic device of the present invention includes a memory core formed on an insulative substrate and implemented by a substance that performs, when a current flows therethrough, electromigration and varies in at least part of its shape or at least p... | 10/21/2003 |
| 6600191 | Method of fabricating conductive straps to interconnect contacts to corresponding digit lines by employing an angled sidewall implant and semiconductor devices fabricated thereby A method for interconnecting bit contacts and digit lines of a semiconductor device. A mask, through which portions of sidewall spacers of the digit lines located proximate the bit contacts are exposed, is positioned over the digit lines. Dopant is direct... | 07/29/2003 |
| 6579757 | Method for fabricating semiconductor device which prevents gates of a peripheral region from being oxidized A method of fabricating a semiconductor device, includes the steps of forming gates in a cell region and in a peripheral region of a substrate, forming a polysilicon layer over an entire surface of the resultant structure, partially removing portions of t... | 06/17/2003 |
| 6576517 | Method for obtaining a multi-level ROM in an EEPROM process flow Presented is a method for obtaining a multi-level ROM in a dual gate EEPROM process flow. The method begins with, on a semiconductor substrate, defining active areas respectively for transistors of ROM cells, transistors of electrically erasable non-volat... | 06/10/2003 |
| 6531393 | Salicide integrated solution for embedded virtual-ground memory A salicide integrate solution for embedded virtual-ground memory of the present invention provides a controlled distance between poly gates. In this way, the spacers formed on the sidewalls of the poly gates become self fill-upon spacers, and the surface ... | 03/11/2003 |
| 6521957 | Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell The invention relates to a method of producing a multi-level memory of the ROM type in a CMOS process of the dual gate type. Specifically, some of the transistors of the ROM cells have their polysilicon layers masked and the ROM cells are then implanted b... | 02/18/2003 |
| 6521499 | Method for forming non-volatile memory with self-aligned contact A method for forming a non-volatile memory is disclosed. The invention uses elevated buried diffusion polysilicon layers (BDPOLY) and spacers to form self-aligned contact so that the process window can be upgraded. The spacers can be used as an etching st... | 02/18/2003 |
| 6426528 | Method of fabricating conductive straps to interconnect contacts to corresponding digit lines by employing an angled sidewall implant and semiconductor devices fabricated thereby A method for interconnecting bit contacts and digit lines of a semiconductor device. A mask, through which portions of sidewall spacers of the digit lines located proximate the bit contacts are exposed, is positioned over the digit lines. Dopant is direct... | 07/30/2002 |
| 6421293 | One-time programmable memory cell in CMOS technology An OTP memory cell in CMOS technology, including a capacitor associated in series with an unbalanced programming transistor, the drain of which is made of a region deeper and less doped than the source.... | 07/16/2002 |
| 6365443 | Method of manufacturing a semiconductor device having data pads formed in scribed area On a semiconductor wafer, there are formed chip areas for storing memory areas, scribe areas for cutting the semiconductor wafer, pads for supplying electric signals from the outside in order to write data into the memory areas, and lead wires for electri... | 04/02/2002 |
| 6329686 | Method of fabricating conductive straps to interconnect contacts to corresponding digit lines by employing an angled sidewall implant and semiconductor devices fabricated thereby A method of interconnecting bit contacts to corresponding digit lines of a semiconductor memory device. The method is particularly useful for fabricating semiconductor memory devices having digit lines that are less than about 0.2 microns wide and spaced ... | 12/11/2001 |
| 6316313 | Method of manufacturing a flash memory device There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that a well resistance and a parasitic capacitance are great and the erase speed of a device is slow in case of the conventional flash memory device, the pr... | 11/13/2001 |
| 6277690 | Elimination of N+ implant from flash technologies by replacement with standard medium-doped-drain (Mdd) implant A method of manufacturing a semiconductor device that eliminates the N+ implant by replacement with resist spacers on n-channel gate structures and a standard Mdd implant. The N+ implant is thereby eliminated from the n-channel trans... | 08/21/2001 |
| 6274438 | Method of manufacturing contact programmable ROM This invention provides contact programmable ROM which shortens TAT. The manufacturing process comprises two steps of: (a) a step in which a plurality of memory cells having gate region 14 and source/drain regions 15A and 15B is formed on a semiconductor subst... | 08/14/2001 |
| 6225167 | Method of generating multiple oxide thicknesses by one oxidation step using NH3 nitridation followed by re-oxidation A method is disclosed to form a plurality of oxides of different thicknesses with one step oxidation. In a first embodiment, a substrate is provided having a high-voltage cell area and a peripheral low-voltage logic area separated by a trench isolation re... | 05/01/2001 |
| 6177313 | Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cell The invention relates to a method of producing a multi-level memory of the ROM type in a CMOS process of the dual gate type. Specifically, some of the transistors of the ROM cells have their polysilicon layers masked and the ROM cells are then implanted b... | 01/23/2001 |
| 6143610 | Method for fabricating high-density semiconductor read-only memory device A semiconductor read-only memory (ROM) device is provided and includes an array of diode-based memory cells for storing binary data. Whether a memory cell of the ROM device is set to a permanently-ON or OFF state, depends upon whether the memory cell is f... | 11/07/2000 |
| 6133095 | Method for creating diffusion areas for sources and drains without an etch step A method for manufacturing a memory array having a plurality of memory cells thereon and diffusion areas therebetween includes the steps of laying down a layer of silicon nitride, defining the diffusion areas and creating diffusion oxides over the diffusi... | 10/17/2000 |
| 6077763 | Process for fabricating a self-aligned contact A process of fabricating self-aligned contacts for a semiconductor memory IC device. The substrate of the memory device has formed thereon gate structures of the memory cell units for the memory device. The gate structures are regularly spaced apart by fi... | 06/20/2000 |
| 6054734 | Non-volatile memory cell having dual gate electrodes A non-volatile memory device in which gate electrodes are formed on an upper surface and a lower surface of the channel via insulating layers, respectively, one of them is used as a read electrode and the other is used as a write electrode, whereby, at a ... | 04/25/2000 |
| 5998267 | Process to manufacture high density ULSI ROM array A compact MOS array including word lines perpendicular to and overlapping bit lines, is fabricated by etching trenches in the underlying silicon and then forming successive bit lines within the trenches and upon the intervening mesas. Subsequent implantat... | 12/07/1999 |
| 5949704 | Stacked read-only memory A stacked ROM device utilizes the same conductivity type for the ROM cells in both the top and the bottom ROM cell matrixes. The stacked ROM device comprises a first ROM cell matrix which comprises conductively doped source and drain lines having a first ... | 09/07/1999 |
| 5940705 | Methods of forming floating-gate FFRAM devices Methods of forming floating-gate ferroelectric random-access-memory (FFRAM) devices include the steps of forming vertically integrated FFRAM unit cells having floating-gate transistors and access transistors positioned at different levels on a semiconduct... | 08/17/1999 |
| 5925917 | Contact programmable ROM and method of manufacturing the same This invention provides contact programmable ROM which shortens TAT. The manufacturing process comprises two steps of: (a) a step in which a plurality of memory cells having gate region 14 and source/drain regions 15A and 15B is formed on a semiconductor subst... | 07/20/1999 |
