Bizarre Patents
A haircutting appliance comprises an enclosed housing having a hollow handle connecting the housing to a vacuum source to carry away cut hairs from a subject's head.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7439580 | Top drain MOSgated device and process of manufacture therefor A trench type top drain MOSgated device has a drain electrode on the die top and a source electrode on the die bottom surface. The device is turned on by a control voltage connected between a drain and a gate region. The device cell has a body short trench and a gat... | 10/21/2008 |
| 7432562 | SRAM devices, and electronic systems comprising SRAM devices The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystallin... | 10/07/2008 |
| 7425744 | Fabricating logic and memory elements using multiple gate layers Various embodiments are directed to different methods and systems relating to design and implementation of memory cells such as, for example, static random access memory (SRAM) cells. In one embodiment, a memory cell may include a first layer of conductive material ... | 09/16/2008 |
| 7417302 | Semiconductor device and method of manufacturing the same In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first ... | 08/26/2008 |
| 7408231 | SRAM memory semiconductor integrated circuit device In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same... | 08/05/2008 |
| 7384839 | SRAM cell with asymmetrical transistors for reduced leakage A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabricatio... | 06/10/2008 |
| 7382026 | Semiconductor memory device and method of manufacturing the same A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor ar... | 06/03/2008 |
| 7378309 | Method of fabricating local interconnects on a silicon-germanium 3D CMOS A method of fabricating local interconnect on a silicon-germanium 3D CMOS includes fabricating an active silicon CMOS device on a silicon substrate. An insulator layer is deposited on the silicon substrate and a seed window is opened through the insulator layer to t... | 05/27/2008 |
| 7375401 | Static random access memory using thin film transistors A semiconductor thin film is formed having a lateral growth region which is a collection of columnar or needle-like crystals extending generally parallel with a substrate. The semiconductor thin film is illuminated with laser light or strong light having equivalent ... | 05/20/2008 |
| 7368788 | SRAM cells having inverters and access transistors therein with vertical fin-shaped active regions Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter ... | 05/06/2008 |
| 7358131 | Methods of forming SRAM constructions The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystallin... | 04/15/2008 |
| 7358556 | SRAM cell structure and manufacturing method thereof A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an openi... | 04/15/2008 |
| 7332780 | Inverter, semiconductor logic circuit, static random access memory and data latch circuit A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type ... | 02/19/2008 |
| 7312490 | Vertical memory device and method Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first... | 12/25/2007 |
| 7306984 | Method of manufacture of a semiconductor integrated circuit device including a plurality of columnar laminates having different spacing in different directions For improving the filing properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X d... | 12/11/2007 |
| 7304352 | Alignment insensitive D-cache cell A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one rea... | 12/04/2007 |
| 7279755 | SRAM cell with improved layout designs A 6T SRAM cell includes a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source, and a second inverter cross-coupled with the first inverter having a second pull-u... | 10/09/2007 |
| 7276753 | Dynamic random access memory cell and fabricating method thereof A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided. The patterned mask layer exposes the deep trench. A deep trench capacitor is formed inside the deep tren... | 10/02/2007 |
| 7271451 | Memory cell structure A memory structure that reduces soft-errors for us in CMOS devices is provided. The memory cell layout utilizes transistors oriented such that the source-to-drain axis is parallel a shorted side of the memory cell. The dimensions of the memory cell are such that it ... | 09/18/2007 |
| 7259431 | Static random access memory using thin film transistors A semiconductor thin film is formed having a lateral growth region which is a collection of columnar or needle-like crystals extending generally parallel with a substrate. The semiconductor thin film is illuminated with laser light or strong light having equivalent ... | 08/21/2007 |
| 7259052 | Manufacture of a semiconductor integrated circuit device including a pluarality of a columnar laminates having different spacing in different directions For improving the filling properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X ... | 08/21/2007 |
| 7244977 | Longitudinal MISFET manufacturing method, longitudinal MISFET, semiconductor storage device manufacturing method, and semiconductor storage device A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory d... | 07/17/2007 |
| 7214990 | Memory cell with reduced soft error rate The present invention includes SRAM memory cells and methods for forming SRAM cells having reduced soft error rate. The SRAM cell includes a first NMOS transistor and a first PMOS transistor having a common gate, and a second NMOS transistor and a second PMOS transi... | 05/08/2007 |
| 7208369 | Dual poly layer and method of manufacture Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method al... | 04/24/2007 |
| 7199433 | Method of manufacturing semiconductor integrated circuit device having capacitor element In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) ... | 04/03/2007 |
| 7189627 | Method to improve SRAM performance and stability A technique is disclosed for increasing the width of a transistor (300) while the transistor itself may be scaled down. The transistor width (382) is increased by forming recesses (352) within shallow trench isolation (STI) regions (328) ... | 03/13/2007 |
| 7187036 | Connection structure for SOI devices A semiconductor contact connection structure and the method for forming the same are disclosed. The connection structure has a first semiconductor device formed on an insulator substrate. A non-conducting gate interconnect layer is formed on the insulator substrate ... | 03/06/2007 |
| 7105900 | Reduced floating body effect static random access memory cells and methods for fabricating the same An SRAM cell that may reduce or eliminate floating body effect when using a SOI and a method for fabricating the same are provided. A floating body of an access transistor of the SRAM is connected to a source region of a driver transistor, for example, through a bod... | 09/12/2006 |
| 6699756 | Four-transistor static-random-access-memory and forming method A method for forming four transistors static-random-access-memory. The method comprises the steps of: providing a substrate which at least comprises a cell region and periphery region, wherein the cell region comprises a first P-type region, a second P-ty... | 03/02/2004 |
| 6700205 | Semiconductor devices having contact plugs and local interconnects Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are comp... | 03/02/2004 |
| 6699742 | Base current reversal SRAM memory cell and method A SRAM memory cell including an access device formed on a storage device is described. The storage device has at least two stable states that may be used to store information. In operation, the access device is switched ON to allow a signal representing d... | 03/02/2004 |
| 6693360 | Static type semiconductor memory device A memory cell of a static type semiconductor memory device includes a gate electrode of an MOS transistor formed on a main surface of semiconductor substrate via an insulator film, an interlayer insulator film covering the gate electrode, a set of contact... | 02/17/2004 |
| 6689649 | Methods of forming transistors An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each cond... | 02/10/2004 |
| 6690053 | Shared contact in a semiconductor device in which DRAMs and SRAMs are combined and method of manufacturing the same The semiconductor device according to the present invention comprises side wall 9 formed over the sidewall of gate wiring 6 of a logic SRAM region, doped polysilicon 18 electrically connecting silicide layer 13 formed over the surface of diffused layer 11... | 02/10/2004 |
| 6690071 | Semiconductor device using junction leak current A first well of a first conductivity type is formed in a partial region of the surface layer of a semiconductor substrate. A MOS transistor is formed in the first well. The MOS transistor has a gate insulating film, a gate electrode, and first and second ... | 02/10/2004 |
| 6686633 | Semiconductor device, memory cell, and processes for forming them A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at lea... | 02/03/2004 |
| 6683353 | Semiconductor integrated circuit device In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated ... | 01/27/2004 |
| 6682982 | Process method for 1T-SRAM A method of forming a cell memory structure including the step of planarizing an HDP/LDP oxide layer lying over a capacitor area. The method provides for the planarization of the cell storage node, good isolation between the transistor and storage node, r... | 01/27/2004 |
| 6683365 | Edge intensive antifuse device structure An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantial... | 01/27/2004 |
| 6674105 | Semiconductor memory device and method of forming the same In accordance with the present invention, the gate length and the gate insulation film thickness are different between the p-channel MOS field effect transistors serving as the driver gates and the n-channel MOS field effect transistors forming the flip f... | 01/06/2004 |
