Class 257/E21.66 - Simultaneous fabrication of periphery and memory cells (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.646. This subclass
No. of patents: 395
Last issue date: 10/07/2008

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Number	Title	Issue Date
RE40532	Non-volatile memory cell and fabrication method Memory cell transistors with back-channel isolation are produced without using an SOI substrate. With the word line stack acting as a mask, the semiconductor material is etched on both sides of the world line, first anisotropically and then isotropically to widen th...	10/07/2008
7432199	Method of fabricating semiconductor device having reduced contact resistance Provided is a method for fabricating a semiconductor device having reduced contact resistance. In the method, gate patterns defining a narrow opening and a wide opening are formed having an upper portion of a predetermined region of a semiconductor substrate. After ...	10/07/2008
7429507	Semiconductor device having both memory and logic circuit and its manufacture A gate insulating film is formed on the principal surface of a semiconductor substrate. A silicon film is formed on the gate insulating film. Impurities are doped in the silicon film. In this case, impurities are doped into the silicon film to make a region of the s...	09/30/2008
7420229	Failure analysis vehicle for yield enhancement with self test at speed burnin capability for reliability testing A test vehicle for evaluating a manufacturing process for integrated circuits that uses a more space efficient layout of library driving cells arranged to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of a...	09/02/2008
7419865	Methods of forming memory circuitry The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sac...	09/02/2008
7390749	Self-aligned pitch reduction A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a se...	06/24/2008
7314803	Method for producing a semiconductor structure In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of g...	01/01/2008
7312490	Vertical memory device and method Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first...	12/25/2007
7306988	Memory cell and method of making the memory cell Methods of making memory devices/cells are disclosed. A memory cell contains first and second electrode layers and a controllably conductive media therebetween. The controllably conductive media contains a copper sulfide-containing passive layer and active layer con...	12/11/2007
7271057	Memory array with overlapping buried digit line and active area and method for forming same A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends f...	09/18/2007
7247903	Semiconductor memory device A semiconductor memory device having a transistor formed on a semiconductor substrate and a capacitor formed on the upper layer of the transistor and electrically connected to the transistor, includes: a cell contact which is formed on a first interlayer insulation ...	07/24/2007
7244981	Scalable high performance non-volatile memory cells using multi-mechanism carrier transport A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate includes a plurality of diffusion regions that are each formed between a pair of planar select gates. In a ...	07/17/2007
7217610	Method for fabricating a semiconductor product with a memory area and a logic area A method for the integration of field-effect transistors for memory and logic applications in a semiconductor substrate is disclosed. The gate dielectric and a semiconductor layer are deposited over the whole area both in the logic region and in the memory region. F...	05/15/2007
7211482	Method of forming a memory cell having self-aligned contact regions A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over ...	05/01/2007
7186617	Methods of forming integrated circuit devices having a resistor pattern and plug pattern that are made from a same material An integrated circuit device is formed by forming a resistor pattern on a substrate. An interlayer dielectric layer is formed on the resistor pattern. The interlayer dielectric layer is patterned to form at least one opening that exposes the resistor pattern. A plug...	03/06/2007
7176078	Nonvolatile semiconductor memory device having strap region and fabricating method thereof In a nonvolatile semiconductor memory device having a memory cell array region and a strap region for providing voltage to the memory cell array region, in the memory cell array region, a plurality of word lines and a plurality of source lines are formed in a row di...	02/13/2007
7163883	Edge seal for a semiconductor device An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copp...	01/16/2007
7141472	Semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry Methods of forming dynamic random access memories (DRAM) are described. In one embodiment, an insulative layer is formed over a substrate having a plurality of conductive lines which extend within a memory array area and a peripheral area outward of the memory array...	11/28/2006
7112454	System and method for reducing shorting in memory cells An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed...	09/26/2006
6909154	Sacrificial annealing layer for a semiconductor device and a method of fabrication Numerous embodiments of a method and apparatus for a sacrificial annealing layer are disclosed. In one embodiment, a method of forming a sacrificial annealing layer for a semiconductor device comprises forming one or more sacrificial layers on at least a portion of ...	06/21/2005
6703673	SOI DRAM having P-doped poly gate for a memory pass transistor An integrated circuit including a DRAM is disclosed, wherein the DRAM includes a memory array including a plurality of pass gate transistors and a plurality of memory elements. The pass gate transistors include a gate material selected to provide a substa...	03/09/2004
6703279	Semiconductor device having contact of Si-Ge combined with cobalt silicide The present invention provides a metal contact of SiGe combined with cobalt silicide and cobalt. The contact resistance is greatly lowered due to both the low Schottky Barrier Height of SiGe and the low sheet resistance of cobalt silicide. The cobalt laye...	03/09/2004
6703306	Methods of fabricating integrated circuit memories including titanium nitride bit lines Integrated circuit memory devices include a memory cell field effect transistor in an integrated circuit substrate, a conductive plug that electrically contacts the memory cell field effect transistor and a titanium nitride bit line that electrically cont...	03/09/2004
6700205	Semiconductor devices having contact plugs and local interconnects Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are comp...	03/02/2004
6699746	Method for manufacturing semiconductor device The present invention discloses a method for manufacturing a semiconductor device. In the method for manufacturing the semiconductor device, a contact plug connected to a predetermined region for a bit line contact and a storage electrode contact is forme...	03/02/2004
6696351	Semiconductor device having a selectively deposited conductive layer A process of production of a semiconductor memory device having a memory array including memory cells and a peripheral circuit on one substrate comprising the process of forming an interlayer insulating layer covering the memory array and peripheral circu...	02/24/2004
6696720	Semiconductor device having stacked capacitor and protection element A semiconductor device of the present invention comprises a capacitor portion composed of a lower electrode, a capacitor insulator film, and an upper electrode sequentially stacked on an inter-layer insulator film on a semiconductor substrate; and a charg...	02/24/2004
6696719	Semiconductor device with improved peripheral resistance element and method for fabricating same A semiconductor device in which a cell capacitor with an MIM or MIS structure is formed using a conductive material with a low resistivity for the upper electrode and a resistance element is formed using a conductive material with high resistance without ...	02/24/2004
6693834	Device and method for detecting alignment of bit lines and bit line contacts in DRAM devices A method and device for detecting alignment of bit lines and bit line contacts in DRAM devices. In the present invention, the test device is disposed in the scribe line region and is formed by the same masks and process as the bit lines and bit line conta...	02/17/2004
6690050	Semiconductor device and its manufacture In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain regions are formed, and contact holes are formed. Side wall ...	02/10/2004
6690054	Capacitor A method for fabricating a capacitor comprises the steps of: forming a lower electrode of a metal over a substrate; forming a capacitor dielectric film of an oxide dielectric film on the lower electrode; depositing a metal film on the capacitor dielectric...	02/10/2004
6690053	Shared contact in a semiconductor device in which DRAMs and SRAMs are combined and method of manufacturing the same The semiconductor device according to the present invention comprises side wall 9 formed over the sidewall of gate wiring 6 of a logic SRAM region, doped polysilicon 18 electrically connecting silicide layer 13 formed over the surface of diffused layer 11...	02/10/2004
6686617	Semiconductor chip having both compact memory and high performance logic A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory regi...	02/03/2004
6686619	Dynamic random access memory with improved contact arrangements A semiconductor integrated circuit device and a manufacturing method therefor provide advantages that undulations are prevented from being produced in polycrystal silicon plugs in bit line contact holes and that the undesired phenomenon of transversally e...	02/03/2004
6686239	Capacitors of semiconductor devices and methods of fabricating the same A capacitor is disposed on a semiconductor substrate and includes an interlayer dielectric layer pattern with first and second openings, which expose the semiconductor substrate in predetermined regions, respectively. A sidewall and a bottom of the first ...	02/03/2004
6683339	Semiconductor memory device having metal contact structure The present invention discloses a semiconductor memory device having a bit line and a metal contact stud, wherein the metal contact stud is formed on a different layer from a layer on which the bit lines are formed....	01/27/2004
6683353	Semiconductor integrated circuit device In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated ...	01/27/2004
6677199	Structure for preventing salicide bridging and method thereof A semiconductor device having a memory array that includes a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, wherein each of the plurality of the word lines is substantially perpendicular to each of the plu...	01/13/2004
6677650	Silicon plugs and local interconnect for embedded memory and system-on-chip (SOC) applications A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten are formed subsequent to polysilicon plugs required for t...	01/13/2004
6674111	Semiconductor device having a logic transistor therein An etch stopper member is formed under a cell plate electrode so as to surround an active region along a periphery of the cell plate electrode. The etch stopper member is formed from a material that is resistant to an etchant of a first interlayer insulat...	01/06/2004

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Class 257/E21.66 - Simultaneous fabrication of periphery and memory cells (EPO)