Class 257/E21.659 - Making word line (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
No. of patents: 71
Last issue date: 09/23/2008

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Number	Title	Issue Date
7427531	Phase change memory devices employing cell diodes and methods of fabricating the same Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the ...	09/23/2008
7425482	Non-volatile memory device and method for fabricating the same A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a plurality of gate structures on a substrate, each gate structure including a first electrode layer for a floating gate; forming a first insulation layer c...	09/16/2008
7410845	Dual-gate device and method A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provide...	08/12/2008
7339239	Vertical NROM NAND flash memory array Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of the present invention include NROM memory cells in high density vert...	03/04/2008
7303971	MSM binary switch memory device A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over...	12/04/2007
7244981	Scalable high performance non-volatile memory cells using multi-mechanism carrier transport A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate includes a plurality of diffusion regions that are each formed between a pair of planar select gates. In a ...	07/17/2007
7226851	Method for manufacturing semiconductor device and non-volatile memory A method for manufacturing semiconductor device is provided. First, a substrate is provided. Then, a plurality of first gate lines disposed in parallel to each other and a first dummy gate line disposed in a direction perpendicular to the first gate lines are formed...	06/05/2007
7211482	Method of forming a memory cell having self-aligned contact regions A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over ...	05/01/2007
7148113	Semiconductor device and fabricating method thereof A method for fabricating a semiconductor device is described. A gate dielectric layer is formed on a substrate, and several gate structures having a gate conductor, a cap layer and spacers are formed on the gate dielectric layer. A mask layer is formed over the subs...	12/12/2006
6696717	Memory cell with vertical transistor and trench capacitor A memory cell with a vertical transistor and a trench capacitor. The memory cell includes a substrate having a trench and a trench capacitor disposed in the lower trench. A control gate, with a p-type polysilicon germanium layer and an overlying p-type po...	02/24/2004
6680501	Semiconductor device A memory cells are arranged at all intersections of a first word line and one line of a bit-line pair and all intersections of a second word line and the other line of the bit-line pair by arranging in parallel the first word line and the second word line...	01/20/2004
6677205	Integrated spacer for gate/source/drain isolation in a vertical array structure Alignment tolerance for a vertical gate transistor device can be relaxed because of a spacer formed adjacent the trench. The gate electrode is formed of two materials that have etch selectivity between them, such that the outer material can be etched a pr...	01/13/2004
6677199	Structure for preventing salicide bridging and method thereof A semiconductor device having a memory array that includes a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, wherein each of the plurality of the word lines is substantially perpendicular to each of the plu...	01/13/2004
6670665	Memory module with improved electrical properties A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of the memory cell array, which dummy memory cells are not used for storing items of information. F...	12/30/2003
6670711	Semiconductor device including low dielectric constant insulating film formed on upper and side surfaces of the gate electrode A semiconductor device having a self-aligned contact structure. To determine the position of a contact plug in a self-aligned manner, silicon nitride films are provided around a gate electrode and a bitline, respectively. Between the gate electrode and bi...	12/30/2003
6642566	Asymmetric inside spacer for vertical transistor A DRAM array having a DRAM cell employing vertical transistors increases electrical reliability and reduces bitline capacitance by use of an asymmetric structure in the connection between the wordline and the transistor, thereby permitting the use of a wi...	11/04/2003
6638801	Semiconductor device and its manufacturing method A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than...	10/28/2003
6638817	Method for fabricating dram cell array not requiring a device isolation layer between cells The present invention relates to a DRAM cell array and a fabrication method thereof, and which includes: a semiconductor substrate on which a plurality of active regions and isolation regions in a rectangular strip shape at a predetermined distance from e...	10/28/2003
6633057	Non-volatile semiconductor memory and fabricating method therefor In a non-volatile semiconductor memory having a peripheral circuit zone and a memory zone including plural memory cells each having a floating gate and a control gate, an interlayer insulator is formed over the control gate of the memory cells and a gate ...	10/14/2003
6627933	Method of forming minimally spaced word lines A method of forming minimally spaced word lines is disclosed. A double exposure technique is employed at the gate formation level. A small trench is defined through gate stack layers by using a tapered etch or spacers to achieve the desired width of the t...	09/30/2003
6620699	Method for forming inside nitride spacer for deep trench device DRAM cell A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched from a semiconductor material, wherein the oxide lines abuts a pad nitride layer, a pad oxide lay...	09/16/2003
6611062	Twisted wordline strapping arrangement A high density wordline strapping arrangement is obtained by routing three primary metal-2 wordline straps in the same space as four polysilicon wordline, and routing the fourth wordline strap in a metal-4 layer over the primary metal-2 wordline straps. S...	08/26/2003
6573136	Isolating a vertical gate contact structure The present invention provides an easy post GC etch treatment that can remove vertical GC residues without affecting the support devices while ensuring a robust GC to vertical gate contact in all alignment scenarios. The conductive vertical gate contact o...	06/03/2003
6566206	Semiconductor structure having more usable substrate area and method for forming same A semiconductor structure includes a first substrate portion having a surface and a first active region disposed in the first substrate portion. An insulator region is disposed on the first substrate portion outside of the first active region and extends ...	05/20/2003
6552382	Scalable vertical DRAM cell structure and its manufacturing methods A scalable vertical DRAM cell structure comprising a scalable trench region and a self-aligned common-drain diffusion region are disclosed by the present invention, in which the scalable trench region comprises a deep-trench region having a vertical trans...	04/22/2003
6548347	Method of forming minimally spaced word lines A method of forming minimally spaced word lines is disclosed. A double exposure technique is employed at the gate formation level. A small trench is defined through gate stack layers by using a tapered etch or spacers to achieve the desired width of the t...	04/15/2003
6548344	Spacer formation process using oxide shield In the formation of a semiconductor structure, where spacer formation is strongly dependent on the structure (e.g. taper), the improvement of a spacer formation on a poly stud planarized to pad nitride where an oxide is formed on top of the poly prior to ...	04/15/2003
6521938	Dynamic-type semiconductor memory device MOS transistors are formed on island-shaped divided element regions of a silicon substrate, and provided with gate electrodes having the same widths as the element regions. Thereafter, capacitor grooves are formed at end portions of the element regions, a...	02/18/2003
6479852	Memory cell having a deep trench capacitor and a vertical channel A semiconductor memory cell has a deep trench capacitor and a vertical transistor formed over the deep trench capacitor. The vertical transistor has a control gate electrode, a source/drain region at opposite sides of the control gate electrode, and a cha...	11/12/2002
6465298	Method of fabricating a semiconductor-on-insulator memory cell with buried word and body lines A memory cell array for a dynamic random access memory (DRAM) includes word and body lines that are buried below the active semiconductor surface in dielectric material in alternating parallel isolation trenches between adjacent ones of the memory cells. ...	10/15/2002
6465299	Semiconductor memory and method for fabricating the same Semiconductor memory and method for fabricating the same, the semiconductor memory including a cell transistor having a trench region formed in a semiconductor substrate and channel regions at sides of the trench region, source/drain regions formed in a b...	10/15/2002
6455886	Structure and process for compact cell area in a stacked capacitor cell array A method for forming, and a structure for a semiconductor device having vertically-oriented transistors connected to stacked capacitor cells, wherein a contact area for the capacitors enables a compact cell. A vertically-oriented transistor is formed in a...	09/24/2002
6429068	Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regio...	08/06/2002
6420748	Borderless bitline and wordline DRAM structure It is a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the wordline. It is still a further object of the present invention to p...	07/16/2002
6410385	ROM-embedded-DRAM A ROM is embedded within an array of DRAM cells by changing a single mask in a DRAM fabrication process to selectively short circuit the DRAM capacitor lower electrode to its own wordline to create a read-only "1" or to the wordline of an adjacent cell to...	06/25/2002
6403430	Semiconductor structure having more usable substrate area and method for forming same A semiconductor structure includes a first substrate portion having a surface and a first active region disposed in the first substrate portion. An insulator region is disposed on the first substrate portion outside of the first active region and extends ...	06/11/2002
6399447	Method of producing dynamic random access memory (DRAM) cell with folded bitline vertical transistor A semiconductor device and a method for forming the semiconductor device, include forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a con...	06/04/2002
6396096	Design layout for a dense memory cell structure A design layout for a memory cell structure is provided that achieves maximized channel length on the active areas, while not constricting the contact area of the capacitor contacts is provided. Specifically, the layout design provides a semiconductor mem...	05/28/2002
6391705	Fabrication method of high-density semiconductor memory cell structure having a trench A high density semiconductor memory device is provided. The memory device includes a transistor and a capacitor formed along the sidewall of a trench. The trench is formed below the crossing of a word line and a bit line. The capacitor is formed by diffus...	05/21/2002
6376294	Method to define poly dog-bone for word line strapping contact at stitch area in embedded DRAM process A method for fabricating a dog-bone in a DRAM device, comprising the following steps. A semiconductor structure having an upper silicon layer with STIs formed therein is provided. The semiconductor structure has a LOGIC region and a DRAM region with a sti...	04/23/2002

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Class 257/E21.659 - Making word line (EPO)