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| Number | Title | Issue Date |
| 7396750 | Method and structure for contacting two adjacent GMR memory bit A method and a structure are provided for improving the contact of two adjacent GMR memory bits. Two adjacent bit ends are connected by utilizing a single via. ... | 07/08/2008 |
| 7381613 | Self-aligned MIM capacitor process for embedded DRAM A semiconductor device includes a group of capacitors and a trench. Each capacitor includes a first conductive material layer, a dielectric layer, and a second conductive material layer. The dielectric layer is located between the first and second conductive materia... | 06/03/2008 |
| 7365384 | Trench buried bit line memory devices and methods thereof A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermo... | 04/29/2008 |
| 7361591 | Method of fabricating semiconductor memory device A method includes preparing a semiconductor substrate having a cell region, a core NMOS region, and a core PMOS region; defining a cell active region, an NMOS active region, and a PMOS active region in the cell region, the core NMOS region, and the core PMOS region,... | 04/22/2008 |
| 7276725 | Bit line barrier metal layer for semiconductor device and process for preparing the same The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose a... | 10/02/2007 |
| 7244676 | Method for fabricating semiconductor device The present invention provides a method for fabricating a semiconductor device capable of securing a bottom contact area of a storage node contact as well as of preventing losses of a bit line hard mask insulation layer. These effects are achieved by planarizing an ... | 07/17/2007 |
| 7183188 | Method for fabricating contact-making connections The invention provides a method for fabricating contact-making connections, having the steps of: a) providing a substrate (101) with electronic circuit units (102a, 102b) arranged thereon, an intermediate layer (103) filling... | 02/27/2007 |
| 7176072 | Strained silicon devices transfer to glass for display applications A method of fabricating strained silicon devices for transfer to glass for display applications includes preparing a wafer having a silicon substrate thereon; forming a relaxed SiGe layer on the silicon substrate; forming a strained silicon layer on the relaxed SiGe... | 02/13/2007 |
| 7045441 | Method for forming a single-crystal silicon layer on a transparent substrate A method for forming a, single-crystal silicon layer on a transparent substrate. A transparent substrate having an amorphous silicon layer formed thereon and a silicon wafer having a hydrogen ion layer formed therein are provided. The silicon wafer is then reversed ... | 05/16/2006 |
| 6700205 | Semiconductor devices having contact plugs and local interconnects Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are comp... | 03/02/2004 |
| 6699746 | Method for manufacturing semiconductor device The present invention discloses a method for manufacturing a semiconductor device. In the method for manufacturing the semiconductor device, a contact plug connected to a predetermined region for a bit line contact and a storage electrode contact is forme... | 03/02/2004 |
| 6696339 | Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices The present invention is directed toward methods of fabricating components for microelectronic devices, microelectronic devices including memory cells or other components, and computers including memory devices. For example, one embodiment is directed tow... | 02/24/2004 |
| 6696336 | Double sided container process used during the manufacture of a semiconductor device A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric la... | 02/24/2004 |
| 6693319 | Container capacitor structure and method of formation thereof Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode ("bottom electrodes") of the container capacitor structure. The etch provides a recess betwee... | 02/17/2004 |
| 6693834 | Device and method for detecting alignment of bit lines and bit line contacts in DRAM devices A method and device for detecting alignment of bit lines and bit line contacts in DRAM devices. In the present invention, the test device is disposed in the scribe line region and is formed by the same masks and process as the bit lines and bit line conta... | 02/17/2004 |
| 6686668 | Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed... | 02/03/2004 |
| 6683339 | Semiconductor memory device having metal contact structure The present invention discloses a semiconductor memory device having a bit line and a metal contact stud, wherein the metal contact stud is formed on a different layer from a layer on which the bit lines are formed.... | 01/27/2004 |
| 6682975 | Semiconductor memory device having self-aligned contact and fabricating method thereof There is provided a method of fabricating a semiconductor memory device having a self-aligned contact, including the steps of forming a plurality of gate electrodes by interposing a gate insulating layer on an active region of a semiconductor substrate in... | 01/27/2004 |
| 6680254 | Method of fabricating bit line and bit line contact plug of a memory cell A memory cell fabrication avoiding bit line encroaching. A first insulating layer and a first masking layer are formed on a semiconductor substrate with a diffused region. The first masking layer and the first insulating layer are defined to form a first ... | 01/20/2004 |
| 6677205 | Integrated spacer for gate/source/drain isolation in a vertical array structure Alignment tolerance for a vertical gate transistor device can be relaxed because of a spacer formed adjacent the trench. The gate electrode is formed of two materials that have etch selectivity between them, such that the outer material can be etched a pr... | 01/13/2004 |
| 6677650 | Silicon plugs and local interconnect for embedded memory and system-on-chip (SOC) applications A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten are formed subsequent to polysilicon plugs required for t... | 01/13/2004 |
| 6677636 | Structure for reducing contact aspect ratios An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line conta... | 01/13/2004 |
| 6670711 | Semiconductor device including low dielectric constant insulating film formed on upper and side surfaces of the gate electrode A semiconductor device having a self-aligned contact structure. To determine the position of a contact plug in a self-aligned manner, silicon nitride films are provided around a gate electrode and a bitline, respectively. Between the gate electrode and bi... | 12/30/2003 |
| 6670238 | Method and structure for reducing contact aspect ratios An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line conta... | 12/30/2003 |
| 6667503 | Semiconductor trench capacitor Since at least a portion of a trench capacitor electrode is formed by a metal, the electrical sheet resistance of the electrode can be lowered, and the signal propagation time prolonged by CR delay can be shortened. This can reduce the read/write time. Th... | 12/23/2003 |
| 6664157 | Semiconductor integrated circuit device and the method of producing the same Plug electrodes of silicon are formed so as to be buried in through holes in a first insulating film, the plug electrodes being electrically connected to the source and drain regions of a MISFET on the main surface of a semiconductor substrate. Then, a se... | 12/16/2003 |
| 6660584 | Selective polysilicon stud growth of 6F2 memory cell manufacturing having a convex upper surface profile A memory cell is defined along first, second, and third orthogonal dimensions and comprises an electrically conductive word line, an electrically conductive bit line, an electrical charge storage structure, a transistor structure, and a bit line contact. ... | 12/09/2003 |
| 6661048 | Semiconductor memory device having self-aligned wiring conductor According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode... | 12/09/2003 |
| 6661051 | Container capacitor structure and method of formation thereof Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode ("bottom electrodes") of the container capacitor structure. The etch provides a recess betwee... | 12/09/2003 |
| 6656801 | Method of fabricating a ferroelectric stacked memory cell The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control e... | 12/02/2003 |
| 6653230 | Semiconductor device having concave electrode and convex electrode and method of manufacturing thereof It is intended to enable simultaneous formation of concave capacitor storage electrodes and a convex bit contact plug electrode and thereby makes it possible to reduce spaces of margins for alignment errors by decreasing the number of lithography steps. G... | 11/25/2003 |
| 6653241 | Methods of forming protective segments of material, and etch stops The invention encompasses a method of forming a protective segment of material. A plurality of at least three conductive lines are provided over a semiconductor substrate. A material is formed over the conductive lines, and a patterned masking layer is fo... | 11/25/2003 |
| 6649501 | Method for forming a bit line for a semiconductor device The present invention discloses a method for forming a bit line of a semiconductor device which can easily perform a contact process of the semiconductor device, by forming parallel rows of I-shaped active regions, a plug poly and a ladder-type bit line. ... | 11/18/2003 |
| 6649466 | Method of forming DRAM circuitry In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising l... | 11/18/2003 |
| 6649510 | Method of forming semiconductor memory device using a double layered capping pattern A method of forming a semiconductor memory device using a double layered capping pattern and a semiconductor memory device formed thereby are provided. A plurality of interconnection patterns are formed on a semiconductor substrate. Each of the interconne... | 11/18/2003 |
| 6649962 | Selective polysilicon stud growth A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped... | 11/18/2003 |
| 6645806 | Methods of forming DRAMS, methods of forming access transistors for DRAM devices, and methods of forming transistor source/drain regions The invention includes a DRAM device. The device has an access transistor construction, and the access transistor construction has a pair of source/drain regions. A halo region is associated with one of the source/drain regions of the access transistor co... | 11/11/2003 |
| 6642093 | Method for manufacturing a semiconductor device According to the present invention, a method for manufacturing a semiconductor device forms a cobalt silicide film 11 on source/drain regions 7a and 7b and a gate electrode 4 of transistors in the logic circuit region, making it possible to form a high-pe... | 11/04/2003 |
| 6642097 | Structure for capacitor-top-plate to bit-line-contact overlay margin A novel method and structure are described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After insulating the FETs with a first insulating layer, a second insulating laye... | 11/04/2003 |
| 6642566 | Asymmetric inside spacer for vertical transistor A DRAM array having a DRAM cell employing vertical transistors increases electrical reliability and reduces bitline capacitance by use of an asymmetric structure in the connection between the wordline and the transistor, thereby permitting the use of a wi... | 11/04/2003 |
