Class 257/E21.657 - Making bit line (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.656. This subclass
No. of patents: 125
Last issue date: 10/07/2008

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Number	Title	Issue Date
7432178	Bit line implant A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A ...	10/07/2008
7414279	Semiconductor device with improved overlay margin and method of manufacturing the same Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation...	08/19/2008
7396751	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes forming a second storage node contact hole with a mask for storage node and securing an overlay margin between a storage node contact hole and a storage node with a hard mask layer that serves as a hard mask...	07/08/2008
7384847	Methods of forming DRAM arrays The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact...	06/10/2008
7365384	Trench buried bit line memory devices and methods thereof A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermo...	04/29/2008
7361550	Methods of fabricating semiconductor memory devices including electrode contact structures having reduced contact resistance A semiconductor memory device includes a semiconductor substrate having an active region therein, an insulating layer on the substrate, and a lower electrode conductive pad extending through the insulating layer. The lower electrode conductive pad electrically conta...	04/22/2008
7339239	Vertical NROM NAND flash memory array Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of the present invention include NROM memory cells in high density vert...	03/04/2008
7335554	Method for fabricating semiconductor A method for fabricating a semiconductor device includes forming a first trench by etching a substrate already provided with a storage node contact (SNC) region and a bit line contact (BLC) region, forming a protection layer on sidewalls of the first trench, forming...	02/26/2008
7332815	Semiconductor device The present invention has an object to provide a semiconductor device, an ID tag, in which delay of signal transmission with conductive layers is controlled. In addition, the other object is that a design method of such a semiconductor device is provided. A s...	02/19/2008
7307005	Wafer bonding with highly compliant plate having filler material enclosed hollow core The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The pr...	12/11/2007
7303971	MSM binary switch memory device A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over...	12/04/2007
7276725	Bit line barrier metal layer for semiconductor device and process for preparing the same The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose a...	10/02/2007
7223997	Thin film transistor array panel A thin film array panel is provided, which includes: a gate line formed on a substrate; a first insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a data line formed on the gate insulating layer and intersecting the ...	05/29/2007
6703306	Methods of fabricating integrated circuit memories including titanium nitride bit lines Integrated circuit memory devices include a memory cell field effect transistor in an integrated circuit substrate, a conductive plug that electrically contacts the memory cell field effect transistor and a titanium nitride bit line that electrically cont...	03/09/2004
6703657	DRAM cell having electrode with protection layer A DRAM cell is provided, along with a method for fabricating such a DRAM cell. A protection layer pattern is formed to cover a common drain region of first and second access transistors. Storage node holes are then formed to expose each source region of t...	03/09/2004
6700205	Semiconductor devices having contact plugs and local interconnects Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are comp...	03/02/2004
6696762	Bi-level digit line architecture for high density DRAMS There is a bi-level bit line architecture. Specifically, there is a DRAM memory cell and cell array that allows for six square feature area (6F2) cell sizes and avoids the signal to noise problems. Uniquely, the digit lines are designed to lie ...	02/24/2004
6696339	Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices The present invention is directed toward methods of fabricating components for microelectronic devices, microelectronic devices including memory cells or other components, and computers including memory devices. For example, one embodiment is directed tow...	02/24/2004
6693834	Device and method for detecting alignment of bit lines and bit line contacts in DRAM devices A method and device for detecting alignment of bit lines and bit line contacts in DRAM devices. In the present invention, the test device is disposed in the scribe line region and is formed by the same masks and process as the bit lines and bit line conta...	02/17/2004
6686668	Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed...	02/03/2004
6680859	Logic process DRAM A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bi...	01/20/2004
6680254	Method of fabricating bit line and bit line contact plug of a memory cell A memory cell fabrication avoiding bit line encroaching. A first insulating layer and a first masking layer are formed on a semiconductor substrate with a diffused region. The first masking layer and the first insulating layer are defined to form a first ...	01/20/2004
6680501	Semiconductor device A memory cells are arranged at all intersections of a first word line and one line of a bit-line pair and all intersections of a second word line and the other line of the bit-line pair by arranging in parallel the first word line and the second word line...	01/20/2004
6680511	Integrated circuit devices providing improved short prevention The present invention provide integrated circuit devices and methods of fabricating the same that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer...	01/20/2004
6677199	Structure for preventing salicide bridging and method thereof A semiconductor device having a memory array that includes a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, wherein each of the plurality of the word lines is substantially perpendicular to each of the plu...	01/13/2004
6670711	Semiconductor device including low dielectric constant insulating film formed on upper and side surfaces of the gate electrode A semiconductor device having a self-aligned contact structure. To determine the position of a contact plug in a self-aligned manner, silicon nitride films are provided around a gate electrode and a bitline, respectively. Between the gate electrode and bi...	12/30/2003
6664585	Semiconductor memory device having multilayered storage node contact plug and method for fabricating the same A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The semiconductor memory device includes a multi-layered stora...	12/16/2003
6665204	Semiconductor memory device for decreasing a coupling capacitance The semiconductor memory device of the present invention comprises: memory cells arranged in a matrix; word lines extending in a row direction; bit line pairs extending in a column direction; exchange blocks for exchanging the bit lines of the different n...	12/16/2003
6660584	Selective polysilicon stud growth of 6F2 memory cell manufacturing having a convex upper surface profile A memory cell is defined along first, second, and third orthogonal dimensions and comprises an electrically conductive word line, an electrically conductive bit line, an electrical charge storage structure, a transistor structure, and a bit line contact. ...	12/09/2003
6649501	Method for forming a bit line for a semiconductor device The present invention discloses a method for forming a bit line of a semiconductor device which can easily perform a contact process of the semiconductor device, by forming parallel rows of I-shaped active regions, a plug poly and a ladder-type bit line. ...	11/18/2003
6649508	Methods of forming self-aligned contact structures in semiconductor integrated circuit devices Methods of forming integrated circuit devices (e.g., memory devices) include the use of preferred self-aligned contact hole fabrication steps. These steps improve process reliability by reducing the likelihood that contact holes will become misaligned to ...	11/18/2003
6649465	Process for manufacturing a semiconductor memory device including a memory cell selecting transistor and a capacitor with metal electrodes A technique is provided which is capable of forming a Ru film constituting a lower electrode of an information storing capacitive element in an aperture with high precision. After a Ru film is deposited, heat treatment is performed in a reducing atmospher...	11/18/2003
6649510	Method of forming semiconductor memory device using a double layered capping pattern A method of forming a semiconductor memory device using a double layered capping pattern and a semiconductor memory device formed thereby are provided. A plurality of interconnection patterns are formed on a semiconductor substrate. Each of the interconne...	11/18/2003
6649962	Selective polysilicon stud growth A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped...	11/18/2003
6638811	Method of manufacturing a semiconductor integrated circuit device having a capacitor In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2 O5 (tantalum oxide) film 46, the portions ...	10/28/2003
6639288	Semiconductor device with a particular conductor arrangement A tungsten nitride (6b) is provided also on side surface of a tungsten (6c), to increase an area where the tungsten (6c) and the tungsten nitride (6b) are in contact with each other. On a gate insulating film (2), a polysilicon side wall (5) having high a...	10/28/2003
6636415	Capacitor constructions, methods of forming bitlines, and methods of forming capacitor and bitline structures The invention encompasses a method of forming bitlines. A substrate is provided, and comprises a plurality of spaced electrical nodes. A bitline layer is formed over at least some of the spaced electrical nodes. The bitline layer comprises at least one co...	10/21/2003
6635933	Structure of a capacitor section of a dynamic random-access memory Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or th...	10/21/2003
6635918	Semiconductor integrated circuit device and method for manufacturing the same The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL1, BL2 are, respectively, 2 Ω/.quadrature. or below. Interconnections of a peripheral circuit a...	10/21/2003
6627931	Ferroelectric memory cell and corresponding manufacturing method Presented is a memory cell integrated in a semiconductor substrate that includes a MOS device connected in series to a capacitive element. The MOS device has first and second conduction terminals, and the capacitive element has a lower electrode covered w...	09/30/2003

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Class 257/E21.657 - Making bit line (EPO)