Class 257/E21.655 - Transistor in U- or V-shaped trench in substrate (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.654. This subclass
No. of patents: 146
Last issue date: 10/21/2008

«First «Previous1 2 3 4 Next»Last»

Number	Title	Issue Date
7439579	Power semiconductor with functional element guide structure A trench transistor is described. In one aspect, the trench transistor has a cell array having a plurality of cell array trenches and a plurality of mesa zones arranged between the cell array trenches, and a semiconductor functional element formed in one of the mesa...	10/21/2008
7419878	Planarized and silicided trench contact Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures i...	09/02/2008
7419871	Methods of forming semiconductor constructions The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array region. Paired transistors are formed within the memory array region, with such paired transistors shari...	09/02/2008
7416948	Trench FET with improved body to gate alignment A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductiv...	08/26/2008
7414279	Semiconductor device with improved overlay margin and method of manufacturing the same Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation...	08/19/2008
7402487	Process for fabricating a semiconductor device having deep trench structures A process for fabricating a semiconductor device having deep trench structures includes forming a first portion of the trench in a semiconductor substrate and a second portion of the trench in a selectively-formed upper layer. After etching the substrate to form the...	07/22/2008
7399673	Method of forming a charge-trapping memory device In a charge-trapping device having an array of memory cells, which are controlled by word lines buried in trenches within a substrate, further trenches are formed parallel to said word lines within said substrate. These subdivide diffusion regions adjacent to the wo...	07/15/2008
7368776	Semiconductor device comprising a highly-reliable, constant capacitance capacitor A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. ...	05/06/2008
7361537	Method of fabricating recess channel array transistor A method of fabricating a recess channel array transistor is disclosed. An impurity region is formed in a semiconductor substrate. Then, a polysilicon layer is formed on the semiconductor substrate, both of which are then etched to form a trench that defines an acti...	04/22/2008
7344954	Method of manufacturing a capacitor deep trench and of etching a deep trench opening A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens...	03/18/2008
7320919	Method for fabricating semiconductor device with metal-polycide gate and recessed channel A method for fabricating a semiconductor device with a metal-polycide gate and a recessed channel, including the steps of: forming trenches for a recessed channel in an active area of a semiconductor substrate; forming a gate insulating layer on the semiconductor su...	01/22/2008
7309634	Non-volatile semiconductor memory devices using prominences and trenches A semiconductor substrate is patterned to form a depression and prominence. A floating gate is formed so as to cover at least both sidewalls of the prominence of the depression and prominence, and is then etched to form a trench for a device isolation self-aligned w...	12/18/2007
7306993	Method for fabricating semiconductor device with recessed channel A method for fabricating a semiconductor device with a recessed channel, including the steps of: forming trenches for a recessed channel in an active area of a semiconductor substrate; forming a gate insulating layer on the semiconductor substrate having the trenche...	12/11/2007
7297596	Method of manufacturing a semiconductor device having a switching function A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer ...	11/20/2007
7294879	Vertical MOSFET with dual work function materials A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical p...	11/13/2007
7276753	Dynamic random access memory cell and fabricating method thereof A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided. The patterned mask layer exposes the deep trench. A deep trench capacitor is formed inside the deep tren...	10/02/2007
7276410	Semiconductor device with omega gate and method for fabricating a semiconductor device A substrate has an active region divided into storage node contact junction regions, channel regions and a bit line contact junction region. Device isolation layers are formed in the substrate isolating the active region from a neighboring active region Recess patte...	10/02/2007
7276752	Methods of forming integrated circuits, and DRAM circuitry memory cells This invention includes methods of forming integrated circuits, and includes DRAM circuitry memory cells. In one implementation, a method of forming an integrated circuit includes forming a trench isolation mask over a semiconductor substrate. The trench isolation m...	10/02/2007
7241658	Vertical gain cell A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a source region, and a second vertical MOS transistor merged with the se...	07/10/2007
7238573	Method for fabricating a trench transistor of semiconductor device A method for fabricating a semiconductor transistor including forming a first insulating layer on a semiconductor substrate; forming an LDD region using ion implantation; patterning the first insulating layer; forming a trench in the substrate; forming a trench gate...	07/03/2007
7220640	Method of fabricating recess transistor in integrated circuit device and recess transistor in integrated circuit device fabricated by the same Provided is a method of fabricating a recess transistor in an integrated circuit device. In the provided method, a device isolation region, which contacts to the sidewall of a gate trench and a substrate region remaining between the sidewall of the device isolation ...	05/22/2007
7157378	Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on...	01/02/2007
7087950	Flash memory cell, flash memory device and manufacturing method thereof The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source-/drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said ch...	08/08/2006
6700826	Semiconductor apparatus A simply structured, and highly reliable semiconductor apparatus having a large storage capacity. The apparatus has a plurality of memory cells on one semiconductor substrate, each including a capacitor having first and second electrodes, and a switching ...	03/02/2004
6696713	Semiconductor memory provided with vertical transistor and method of manufacturing the same There is proposed a vertical cell transfer transistor comprising a channel region constituted by a monocrystalline silicon layer which is formed by way of epitaxial growth, source-drain regions constituted by n-type diffusion regions which are formed over...	02/24/2004
6689660	4 F2 folded bit line DRAM cell structure having buried bit and word lines A memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines. Isolation trenches extend orthogonal...	02/10/2004
6680501	Semiconductor device A memory cells are arranged at all intersections of a first word line and one line of a bit-line pair and all intersections of a second word line and the other line of the bit-line pair by arranging in parallel the first word line and the second word line...	01/20/2004
6677205	Integrated spacer for gate/source/drain isolation in a vertical array structure Alignment tolerance for a vertical gate transistor device can be relaxed because of a spacer formed adjacent the trench. The gate electrode is formed of two materials that have etch selectivity between them, such that the outer material can be etched a pr...	01/13/2004
6664806	Memory address and decode circuits with ultra thin body transistors A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. The decoder includes a number of vertical pillars extending outwardly from ...	12/16/2003
6656807	Grooved planar DRAM transfer device using buried pocket A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion incl...	12/02/2003
6645808	Method and device for providing double cell density in SDRAM and in DDR SDRAM Method and device for providing double cell density in synchronous dynamic random access memory (SDRAM) and in double data rate synchronous dynamic random access memory (DDR SDRAM) are disclosed. In specific embodiments, a conventional photolithography te...	11/11/2003
6642566	Asymmetric inside spacer for vertical transistor A DRAM array having a DRAM cell employing vertical transistors increases electrical reliability and reduces bitline capacitance by use of an asymmetric structure in the connection between the wordline and the transistor, thereby permitting the use of a wi...	11/04/2003
6638812	Method for producing a memory cell for a semiconductor memory The method of the invention, in contrast to conventional trench capacitors wherein the memory node is formed in a trench, normally in the form of a drilled hole, includes the steps of forming the memory node in the monocrystalline silicon of the substrate...	10/28/2003
6627940	Memory cell arrangement A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in ...	09/30/2003
6621725	Semiconductor memory device with floating storage bulk region and method of manufacturing the same A memory cell MC comprises one MOS transistor having a floating bulk region which is electrically isolated from others. A gate electrode 13 of the MOS transistor is connected to a word line WL, a drain diffusion region 14 thereof is connected to a bit lin...	09/16/2003
6620677	Support liner for isolation trench height control in vertical DRAM processing A method of manufacturing a vertical DRAM device (10) having isolation trenches (38) with a controlled height. A support liner (54) is disposed over support regions (18) of a wafer. A first insulating layer is disposed over the wafer, and the first insula...	09/16/2003
6620699	Method for forming inside nitride spacer for deep trench device DRAM cell A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched from a semiconductor material, wherein the oxide lines abuts a pad nitride layer, a pad oxide lay...	09/16/2003
6614074	Grooved planar DRAM transfer device using buried pocket A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion incl...	09/02/2003
6610573	Method for forming a single wiring level for transistors with planar and vertical gates on the same substrate A memory cell comprises a region containing one or more vertical pass transistor, and a support region containing, e.g. one or more planar transistors. During processing, a polysilicon layer is formed for the planar devices gate. The polysilicon layer is ...	08/26/2003
6603168	Vertical DRAM device with channel access transistor and stacked storage capacitor and associated method An integrated circuit memory device includes a substrate having at least one connection line therein and a plurality of memory cells formed on the substrate. Each memory cell includes a pillar comprising a lower source/drain region for a cell access trans...	08/05/2003

«First «Previous1 2 3 4 Next»Last»

PatentStorm

Quotables

PatentStorm News

Class 257/E21.655 - Transistor in U- or V-shaped trench in substrate (EPO)