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| Number | Title | Issue Date |
| 7365403 | Semiconductor topography including a thin oxide-nitride stack and method for making the same A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes grow... | 04/29/2008 |
| 7232705 | Integrated circuit bond pad structures and methods of making A bond pad structure for an integrated circuit includes first and second active devices formed in a substrate, first and second buses above the first and second active devices, respectively, a bond pad above the first and second buses, first interconnections between... | 06/19/2007 |
| 7091588 | Semiconductor device including primary and secondary side circuits on first and second substrates with capacitive insulation A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while... | 08/15/2006 |
| 6909154 | Sacrificial annealing layer for a semiconductor device and a method of fabrication Numerous embodiments of a method and apparatus for a sacrificial annealing layer are disclosed. In one embodiment, a method of forming a sacrificial annealing layer for a semiconductor device comprises forming one or more sacrificial layers on at least a portion of ... | 06/21/2005 |
| 6703279 | Semiconductor device having contact of Si-Ge combined with cobalt silicide The present invention provides a metal contact of SiGe combined with cobalt silicide and cobalt. The contact resistance is greatly lowered due to both the low Schottky Barrier Height of SiGe and the low sheet resistance of cobalt silicide. The cobalt laye... | 03/09/2004 |
| 6703673 | SOI DRAM having P-doped poly gate for a memory pass transistor An integrated circuit including a DRAM is disclosed, wherein the DRAM includes a memory array including a plurality of pass gate transistors and a plurality of memory elements. The pass gate transistors include a gate material selected to provide a substa... | 03/09/2004 |
| 6699755 | Method for producing a gate A method for producing a gate on a semiconductor substrate. The semiconductor substratehas a first oxide layer, a conductive layer, a silicide layer, and a hard mask formed thereon. The method includes defining the hard mask to form a pattern of the gate,... | 03/02/2004 |
| 6693018 | Method for fabricating DRAM cell transistor having trench isolation structure The present invention relates to a method for fabricating a DRAM cell transistor having a trench isolation structure, which can prevent the reduction in effective channel length and the deterioration of a punch-through characteristic at the edge portion o... | 02/17/2004 |
| 6690050 | Semiconductor device and its manufacture In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain regions are formed, and contact holes are formed. Side wall ... | 02/10/2004 |
| 6683353 | Semiconductor integrated circuit device In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated ... | 01/27/2004 |
| 6677633 | Semiconductor device In manufacturing a semiconductor memory by using conventional gain cells, it is difficult to integrate them similarly to 1T1C cells of a DRAM if mask alignment accuracy is considered. In order to achieve integration similarly to that of 1T1C cells by usin... | 01/13/2004 |
| 6670682 | Multilayered doped conductor A memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making are disclosed. The multilayered doped conductor creates a high dopant concentration in the active area close to the c... | 12/30/2003 |
| 6670664 | Single transistor random access memory (1T-RAM) cell with dual threshold voltages A random access memory cell and a method for fabrication thereof provide a field effect transistor device laterally adjoining a metal oxide semiconductor capacitor device, each formed within an active region of a semiconductor substrate. Within the random... | 12/30/2003 |
| 6670253 | Fabrication method for punch-through defect resistant semiconductor memory device A semiconductor device and a fabrication method thereof which can, for example, prevent a punch-through from occurring by forming oxide spacers around source/drain regions in a semiconductor substrate instead of forming a conventional halo ion implanting ... | 12/30/2003 |
| 6670667 | Asymmetric gates for high density DRAM A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment... | 12/30/2003 |
| 6664589 | Technique to control tunneling currents in DRAM capacitors, cells, and devices Structure and methods for the use of PMOS devices, with p-type polysilicon gates or metal gates with large electron affinities or work functions are provided. These PMOS devices minimize tunneling leakage currents in DRAM capacitors, cells and devices, as... | 12/16/2003 |
| 6661699 | Random access memory cell having double-gate access transistor for reduced leakage current A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell (300) includes a storage capacitor (304) and a pass transistor (302). The pass transistor (302) includes a source region (322), drain region (320) and channel reg... | 12/09/2003 |
| 6661702 | Double gate DRAM memory cell having reduced leakage current A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell (300) includes a storage capacitor (304) and a pass transistor (302). The pass transistor (302) includes a source region (322), drain region (320) and channel reg... | 12/09/2003 |
| 6661055 | Transistor in semiconductor devices The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. According to the present invention, the transistor has an auxiliary electrode to which a voltage is applied apart from a gate electrode and forme... | 12/09/2003 |
| 6657265 | Semiconductor device and its manufacturing method A semiconductor device includes metal silicide films formed on the surface of a source-drain region and of a gate electrode. On the metal silicide films, impurity regions are formed of a conductivity type opposite to the conductivity type of the source-dr... | 12/02/2003 |
| 6653675 | Dual gate dielectric construction Dual gate dielectric constructions and methods therefor are disclosed for different regions on an integrated circuit. In the illustrated embodiment, gate dielectrics in memory array regions of the chip are formed of silicon oxide, while the gate dielectri... | 11/25/2003 |
| 6654295 | Reduced topography DRAM cell fabricated using a modified logic process and method for operating same A memory system that includes a DRAM cell that includes an access transistor and a storage capacitor. The storage capacitor is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate... | 11/25/2003 |
| 6649467 | Method of making high density semiconductor memory A dynamic random access memory (DRAM) includes a plurality of memory cells aligned with one another along a pair of wordlines with each wordline being connected to access alternate ones of the memory cells. The DRAM memory cells are formed by transistor s... | 11/18/2003 |
| 6649510 | Method of forming semiconductor memory device using a double layered capping pattern A method of forming a semiconductor memory device using a double layered capping pattern and a semiconductor memory device formed thereby are provided. A plurality of interconnection patterns are formed on a semiconductor substrate. Each of the interconne... | 11/18/2003 |
| 6645806 | Methods of forming DRAMS, methods of forming access transistors for DRAM devices, and methods of forming transistor source/drain regions The invention includes a DRAM device. The device has an access transistor construction, and the access transistor construction has a pair of source/drain regions. A halo region is associated with one of the source/drain regions of the access transistor co... | 11/11/2003 |
| 6642098 | DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolat... | 11/04/2003 |
| 6638805 | Method of fabricating a DRAM semiconductor device A method of fabricating a DRAM semiconductor device including forming gate stacks in which a gate pattern and a gate sacrificial mask are sequentially deposited on a semiconductor substrate, forming an etch stopper on the semiconductor substrate, forming ... | 10/28/2003 |
| 6638801 | Semiconductor device and its manufacturing method A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than... | 10/28/2003 |
| 6639264 | Method and structure for surface state passivation to improve yield and reliability of integrated circuit structures A method for passivating surface states in an integrated circuit structure having a gate conductor with a gate dielectric layer. The method comprises the step of fabricating a solid state source of fluorine in close proximity to the gate dielectric layer.... | 10/28/2003 |
| 6635933 | Structure of a capacitor section of a dynamic random-access memory Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or th... | 10/21/2003 |
| 6635536 | Method for manufacturing semiconductor memory device A method for manufacturing a semiconductor memory device is disclosed. A spacer of a material having a high etching selection ratio with respect to an interdielectric layer is formed on a sidewall of a gate electrode. A refractory metal silicide layer is ... | 10/21/2003 |
| 6635538 | Method of manufacturing a semiconductor device When sidewalls (10) are formed by anisotropic etching, an insulating film (9) serves as a protective film for a major surface of a semiconductor substrate (100) and therefore prevents the major surface from suffering etching damage. That relieves an elect... | 10/21/2003 |
| 6635918 | Semiconductor integrated circuit device and method for manufacturing the same The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL1, BL2 are, respectively, 2 Ω/.quadrature. or below. Interconnections of a peripheral circuit a... | 10/21/2003 |
| 6635540 | Method for using thin spacers and oxidation in gate oxides A method for forming a lightly doped drain (LDD) field effect transistor uses very thin first sidewall spacers over the gate sidewalls, in which annealing/oxidation of the sidewall spacers results in (a) the rounding of corner portions of the gate structu... | 10/21/2003 |
| 6630706 | Localized array threshold voltage implant to enhance charge storage within DRAM memory cells A DRAM device having improved charge storage capabilities and methods for providing the same. The device includes an array portion having a plurality of memory cells extending from a semiconductor substrate. Each cell includes a storage element for storin... | 10/07/2003 |
| 6630378 | Method of fabricating a dynamic random access memory device having stacked capacitor memory cell arrays A method of forming stacked capacitors over first field effect transistors having been provided in a memory cell area of a semiconductor memory device and at least a second field effect transistor in a peripheral circuit area of the semiconductor memory d... | 10/07/2003 |
| 6628551 | Reducing leakage current in memory cells A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The access transistors are high gate threshold voltage transistors to reduce leakage current in the memory cell. The gate threshold voltage of the acces... | 09/30/2003 |
| 6627933 | Method of forming minimally spaced word lines A method of forming minimally spaced word lines is disclosed. A double exposure technique is employed at the gate formation level. A small trench is defined through gate stack layers by using a tapered etch or spacers to achieve the desired width of the t... | 09/30/2003 |
| 6627937 | Semiconductor memory device The present invention contemplates a highly reliable semiconductor memory device. The semiconductor memory device includes a silicon substrate containing a p impurity of a first concentration, an epitaxial layer formed at the silicon substrate and contain... | 09/30/2003 |
| 6624065 | Method of fabricating a semiconductor device using a damascene metal gate A method of fabricating a semiconductor device using a damascene metal gate including the steps of forming a damascene gate oxide layer and a damascene gate electrode on a semiconductor substrate, forming a trench at an upper part of the damascene gate el... | 09/23/2003 |
