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| Number | Title | Issue Date |
| 7439135 | Self-aligned body contact for a semiconductor-on-insulator trench device and method of fabricating same A structure and method of forming a body contact for an semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and exten... | 10/21/2008 |
| 7276752 | Methods of forming integrated circuits, and DRAM circuitry memory cells This invention includes methods of forming integrated circuits, and includes DRAM circuitry memory cells. In one implementation, a method of forming an integrated circuit includes forming a trench isolation mask over a semiconductor substrate. The trench isolation m... | 10/02/2007 |
| 7262092 | High-voltage CMOS-compatible capacitors A high-voltage stacked capacitor includes a first capacitor and a second capacitor. Each capacitor includes a first plate having a first semiconductive body and a second plate having a floating electrode. The first and second semiconductive bodies are electrically i... | 08/28/2007 |
| 7223651 | Dram memory cell with a trench capacitor and method for production thereof A memory cell includes a selection transistor and a trench capacitor. The trench capacitor is filled with a conductive trench filling on which an insulating covering layer is arranged. The insulating covering layer is laterally overgrown, proceeding from the substra... | 05/29/2007 |
| 7208373 | Method of forming a memory cell array and a memory cell array A method of forming a memory cell array comprising a plurality of memory cells, each of the memory cells including a trench capacitor and a transistor is disclosed. In one embodiment, during the formation of the transistors, after the definition of isolation trenche... | 04/24/2007 |
| 7195973 | Method for fabricating a trench capacitor with an insulation collar and corresponding trench capacitor The present invention provides a method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, in particular for a semiconductor memory cell with a planar select... | 03/27/2007 |
| 7192825 | Semiconductor memory device and method for fabricating the same The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in... | 03/20/2007 |
| 6873000 | Storage cell field and method of producing the same A storage cell field has a plurality of storage cells formed in a substrate of a first doping type, said storage cells comprising a trench capacitor arranged in said substrate and a selection transistor associated with said trench capacitor and provided with a trans... | 03/29/2005 |
| 6696335 | Method for forming a diffusion region For particularly simple and targeted formations of a diffusion region, an interfacial region of a semiconductor substrate is subjected to a thermal transformation process and thereby carry out the thermally activated diffusion of a dopant in a substantial... | 02/24/2004 |
| 6696717 | Memory cell with vertical transistor and trench capacitor A memory cell with a vertical transistor and a trench capacitor. The memory cell includes a substrate having a trench and a trench capacitor disposed in the lower trench. A control gate, with a p-type polysilicon germanium layer and an overlying p-type po... | 02/24/2004 |
| 6689656 | Dynamic random access memory and the method for fabricating thereof The present invention discloses a dynamic random access memory and the method for fabricating thereof. A first silicon substrate having a trench capacitor and a second silicon substrate having a transistor are formed with a double layer, which is interpos... | 02/10/2004 |
| 6680237 | Method of manufacturing deep trench capacitor A method of manufacturing a deep trench capacitor. A deep trench is formed in a substrate. A conformal capacitor dielectric layer and a first conductive layer are sequentially formed, completely filling the deep trench. The first conductive layer has a se... | 01/20/2004 |
| 6667503 | Semiconductor trench capacitor Since at least a portion of a trench capacitor electrode is formed by a metal, the electrical sheet resistance of the electrode can be lowered, and the signal propagation time prolonged by CR delay can be shortened. This can reduce the read/write time. Th... | 12/23/2003 |
| 6667504 | Self-aligned buried strap process using doped HDP oxide The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capaci... | 12/23/2003 |
| 6661049 | Microelectronic capacitor structure embedded within microelectronic isolation region Within a method for fabricating a capacitor structure, and a capacitor structure fabricated employing the method, there is formed within an isolation region adjoining an active region of a semiconductor substrate a laterally asymmetric trench which leaves... | 12/09/2003 |
| 6660582 | Method of forming a vertical field-effect transistor device It is proposed when forming field-effect transistor devices in a semiconductor substrate for the overlapping region of a source-drain region that is to be provided to be formed directly as a material region, in particular with outdiffusion processes being... | 12/09/2003 |
| 6653678 | Reduction of polysilicon stress in trench capacitors A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is ... | 11/25/2003 |
| 6635525 | Method of making backside buried strap for SOI DRAM trench capacitor In SOI integrated circuits having trench capacitor DRAM arrays, the decreasing thickness of the insulating layer causes cross-talk between the passing wordline traveling over the trench capacitor. Increasing the depth of the recess at the top of the trenc... | 10/21/2003 |
| 6624033 | Trench DRAM cell with vertical device and buried word lines A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is loc... | 09/23/2003 |
| 6621112 | DRAM with vertical transistor and trench capacitor memory cells and methods of fabrication A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel regio... | 09/16/2003 |
| 6605838 | Process flow for thick isolation collar with reduced length A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The verti... | 08/12/2003 |
| 6605504 | Method of manufacturing circuit with buried strap including a liner Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.... | 08/12/2003 |
| 6593612 | Structure and method for forming a body contact for vertical transistor cells A semiconductor memory cell, in accordance with the present invention includes a deep trench formed in a substrate. The deep trench includes a storage node in a lower portion of the deep trench, and a gate conductor formed in an upper portion of the deep ... | 07/15/2003 |
| 6590249 | One-transistor memory cell configuration and method for its fabrication In a method for fabricating a dynamic memory cell in a semiconductor substrate having a trench capacitor 1 and a selection transistor 2 and a semiconductor memory having such a memory cell, a dielectric insulator layer 17, 201 is formed between the select... | 07/08/2003 |
| 6590248 | Dynamic random access memory and the method for fabricating thereof The present invention discloses a dynamic random access memory and the method for fabricating thereof. A first silicon substrate having a trench capacitor and a second silicon substrate having a transistor are formed with a double layer, which is interpos... | 07/08/2003 |
| 6590258 | SIO stacked DRAM logic A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator... | 07/08/2003 |
| 6579758 | Method and installation for fabricating one-sided buried straps Buried straps are produced on one side in deep trench structures. A PVD process is used to deposit masking material in the recess inclined at an angle. As a result, a masking wedge is produced on the buried strap, on one side in the base region of the rec... | 06/17/2003 |
| 6566190 | Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially low... | 05/20/2003 |
| 6548850 | Trench capacitor configuration and method of producing it A trench capacitor is formed in a substrate and includes a trench having an upper region and a lower region. An insulating collar is formed in the upper region of the trench. The lower region of the trench extends through a buried well. A buried plate is ... | 04/15/2003 |
| 6544837 | SOI stacked DRAM logic A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator... | 04/08/2003 |
| 6537873 | Integrated circuit comprising a memory cell of the DRAM type, and fabrication process The integrated circuit comprises a semiconductor substrate SB supporting a memory cell PM of the DRAM type comprising an access transistor T and a storage capacitor TRC. The access transistor is made on the substrate, and the substrate includes a capaciti... | 03/25/2003 |
| 6518119 | Strap with intrinsically conductive barrier Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of intrinsically conductive recrystallization barrier layers. The intrinsically conductive layers are preferably used adjacent to con... | 02/11/2003 |
| 6518613 | Memory cell configuration with capacitor on opposite surface of substrate and method for fabricating the same A MOS transistor of a memory cell and a bit line connected thereto are disposed on a first surface of a substrate. A capacitor of the memory cell is disposed on a second surface of the substrate, the second surface being opposite to the first surface. A c... | 02/11/2003 |
| 6503798 | Low resistance strap for high density trench DRAMS A method and structure for a dynamic random access device which includes a substrate having a trench, a conductor in the trench, a transistor adjacent the trench and a conductive strap electrically connecting the conductor and the transistor, wherein the ... | 01/07/2003 |
| 6500707 | Method for manufacturing a trench capacitor of a memory cell of a semiconductor memory A trench is formed in a substrate with an upper region and a lower region. The trench is subsequently widened in its upper region and in its lower region by isotropic etching. In the upper region, an insulating collar is formed that is designated as a bur... | 12/31/2002 |
| 6501117 | Static self-refreshing DRAM structure and operating mode A DRAM cell storage capacitor is formed above the bottom of a deep trench (DT) below an FET transistor. The DT has upper, central and lower portions with sidewalls. A capacitor plate electrode, surrounding the lower DT portion that is doped with a first d... | 12/31/2002 |
| 6448600 | DRAM cell configuration and fabrication method The memory cells each have a capacitor and a transistor. A storage node of the capacitor is arranged in a first depression formed in a substrate. A gate electrode of the transistor is arranged in a second depression at a first lateral surface of the secon... | 09/10/2002 |
| 6440872 | Method for hybrid DRAM cell utilizing confined strap isolation A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.... | 08/27/2002 |
| 6440794 | Method for forming an array of DRAM cells by employing a self-aligned adjacent node isolation technique In a method for forming an array of dynamic random access memory (DRAM) cells, each DRAM cell having one or more field effect transistors (FETs) and a deep trench capacitor, first, a substrate is prepared. Line type active areas (AAs) are patterned on the... | 08/27/2002 |
| 6426253 | Method of forming a vertically oriented device in an integrated circuit A system and method of forming an electrical connection (142) to the interior of a deep trench (104) in an integrated circuit utilizing a low-angle dopant implantation (114) to create a self-aligned mask over the trench. The electrical connection preferab... | 07/30/2002 |
