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| Number | Title | Issue Date |
| 7439135 | Self-aligned body contact for a semiconductor-on-insulator trench device and method of fabricating same A structure and method of forming a body contact for an semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and exten... | 10/21/2008 |
| 7429509 | Method for forming a semiconductor device A method for forming a semiconductor device. A substrate is provided, wherein the substrate has recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers ... | 09/30/2008 |
| 7394124 | Dynamic random access memory device A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer ... | 07/01/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7358133 | Semiconductor device and method for making the same A method for forming a semiconductor device is provided. The method comprises providing a substrate with recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed.... | 04/15/2008 |
| 7354822 | Method of forming a MOSFET with dual work function materials A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical p... | 04/08/2008 |
| 7316953 | Method for forming a recessed gate with word lines A method for forming a semiconductor device. A substrate is provided, wherein the substrate has recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers ... | 01/08/2008 |
| 7316952 | Method for forming a memory device with a recessed gate A method for forming a semiconductor device. A substrate, having a plurality of deep trench capacitors therein, is provided wherein upper portions of the deep trench capacitor devices are revealed. Spacers on sidewalls of the upper portions of the deep trench capaci... | 01/08/2008 |
| 7276754 | Annular gate and technique for fabricating an annular gate A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surfac... | 10/02/2007 |
| 7229872 | Low voltage power MOSFET device and process for its manufacture A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capaci... | 06/12/2007 |
| 7115934 | Method and structure for enhancing trench capacitance A trench capacitor formed with a bottle etch step has a polygonal cross section produced by forming thermally oxidizing the trench walls with thinner oxide at the corners of the trench, then performing the bottle etch step with the nitride in place, thereby extendin... | 10/03/2006 |
| 6696335 | Method for forming a diffusion region For particularly simple and targeted formations of a diffusion region, an interfacial region of a semiconductor substrate is subjected to a thermal transformation process and thereby carry out the thermally activated diffusion of a dopant in a substantial... | 02/24/2004 |
| 6696717 | Memory cell with vertical transistor and trench capacitor A memory cell with a vertical transistor and a trench capacitor. The memory cell includes a substrate having a trench and a trench capacitor disposed in the lower trench. A control gate, with a p-type polysilicon germanium layer and an overlying p-type po... | 02/24/2004 |
| 6680864 | Method for reading a vertical gain cell and array for a dynamic random access memory A vertical gain memory cell including an n-channel metal-oxide semiconductor field-effect transistor (MOSFET) and p-channel junction field-effect transistor (JFET) transistors formed in a vertical pillar of semiconductor material is provided. The body por... | 01/20/2004 |
| 6680501 | Semiconductor device A memory cells are arranged at all intersections of a first word line and one line of a bit-line pair and all intersections of a second word line and the other line of the bit-line pair by arranging in parallel the first word line and the second word line... | 01/20/2004 |
| 6677205 | Integrated spacer for gate/source/drain isolation in a vertical array structure Alignment tolerance for a vertical gate transistor device can be relaxed because of a spacer formed adjacent the trench. The gate electrode is formed of two materials that have etch selectivity between them, such that the outer material can be etched a pr... | 01/13/2004 |
| 6667504 | Self-aligned buried strap process using doped HDP oxide The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capaci... | 12/23/2003 |
| 6660582 | Method of forming a vertical field-effect transistor device It is proposed when forming field-effect transistor devices in a semiconductor substrate for the overlapping region of a source-drain region that is to be provided to be formed directly as a material region, in particular with outdiffusion processes being... | 12/09/2003 |
| 6645808 | Method and device for providing double cell density in SDRAM and in DDR SDRAM Method and device for providing double cell density in synchronous dynamic random access memory (SDRAM) and in double data rate synchronous dynamic random access memory (DDR SDRAM) are disclosed. In specific embodiments, a conventional photolithography te... | 11/11/2003 |
| 6642566 | Asymmetric inside spacer for vertical transistor A DRAM array having a DRAM cell employing vertical transistors increases electrical reliability and reduces bitline capacitance by use of an asymmetric structure in the connection between the wordline and the transistor, thereby permitting the use of a wi... | 11/04/2003 |
| 6638815 | Formation of self-aligned vertical connector In a vertical-transistor based semiconductor structure, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a sacrificial insulato... | 10/28/2003 |
| 6638812 | Method for producing a memory cell for a semiconductor memory The method of the invention, in contrast to conventional trench capacitors wherein the memory node is formed in a trench, normally in the form of a drilled hole, includes the steps of forming the memory node in the monocrystalline silicon of the substrate... | 10/28/2003 |
| 6635526 | Structure and method for dual work function logic devices in vertical DRAM process Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56 cover the dram array 12 and a gate oxide layer 42 and an undoped polysilicon layer 44 cover the su... | 10/21/2003 |
| 6630379 | Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor... | 10/07/2003 |
| 6624033 | Trench DRAM cell with vertical device and buried word lines A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is loc... | 09/23/2003 |
| 6620699 | Method for forming inside nitride spacer for deep trench device DRAM cell A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched from a semiconductor material, wherein the oxide lines abuts a pad nitride layer, a pad oxide lay... | 09/16/2003 |
| 6610573 | Method for forming a single wiring level for transistors with planar and vertical gates on the same substrate A memory cell comprises a region containing one or more vertical pass transistor, and a support region containing, e.g. one or more planar transistors. During processing, a polysilicon layer is formed for the planar devices gate. The polysilicon layer is ... | 08/26/2003 |
| 6610566 | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor A circuit and method for a memory cell with a vertical transistor and a trench capacitor. The cell includes an access transistor that is formed in a pillar of a single crystal semiconductor material. The transistor has vertically aligned first and second ... | 08/26/2003 |
| 6608340 | Substrate assembly having a depression suitable for an integrated circuit configuration and method for its fabrication A depression extends from a main surface of the substrate to the inside of said substrate and has an upper area and an adjacent lower area. A cross-section of the upper area, parallel to the main surface, is provided with at least one corner. A cross-sect... | 08/19/2003 |
| 6605860 | Semiconductor structures and manufacturing methods A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallograph... | 08/12/2003 |
| 6590259 | Semiconductor device of an embedded DRAM on SOI substrate A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator ("SOI") ... | 07/08/2003 |
| 6586795 | DRAM cell configuration whose memory cells can have transistors and capacitors with improved electrical properties Memory cells each include one transistor and one capacitor. A memory node of the capacitor is disposed in a first indentation, while a gate electrode of the transistor is disposed in a second indentation. An upper source/drain region, a channel region, an... | 07/01/2003 |
| 6583462 | Vertical DRAM having metallic node conductor A dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a metallic storage node conductor formed in the lower... | 06/24/2003 |
| 6576944 | Self-aligned nitride pattern for improved process window A device and method for fabricating a gate structure are disclosed. A first conductive material is deposited in a trench formed in a substrate and the first conductive material is recessed to a level below a top surface of the substrate in the trench. A d... | 06/10/2003 |
| 6573561 | Vertical MOSFET with asymmetrically graded channel doping Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are unaffected in a transistor having a vertically asymmetric threshold implant. A preferred embodiment ha... | 06/03/2003 |
| 6573137 | Single sided buried strap A method for clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A barrier material is deposited above a node conducto... | 06/03/2003 |
| 6570208 | 6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. ... | 05/27/2003 |
| 6566193 | Method for producing a cell of a semiconductor memory The process first forms trench capacitors in a substrate, which are filled with a trench fill and in which a first insulating layer is disposed over the conductive trench fill. The first insulating layer is then overgrown laterally by a selectively grown ... | 05/20/2003 |
| 6566227 | Strap resistance using selective oxidation to cap DT poly before STI etch A method of providing shallow trench (143) isolation for a semiconductor wafer (100). Trenches (113) are formed within a first semiconductor material (112) and a pad nitride (114), leaving a portion of first semiconductor material (112) and pad nitride (1... | 05/20/2003 |
| 6566177 | Silicon-on-insulator vertical array device trench capacitor DRAM A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer i... | 05/20/2003 |
