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| Number | Title | Issue Date |
| 7432165 | Semiconductor memory device, semiconductor device, and method for production thereof Disclosed are a semiconductor memory device, a semiconductor device, and a method for production thereof. The semiconductor memory device and semiconductor device do not need for a distance for alignment of lithography to make the contact hole with lithography to fo... | 10/07/2008 |
| 7416943 | Peripheral gate stacks and recessed array gates Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate ... | 08/26/2008 |
| 7402488 | Method of manufacturing a semiconductor memory device A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of t... | 07/22/2008 |
| 7387939 | Methods of forming semiconductor structures and capacitor devices The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor elect... | 06/17/2008 |
| 7355234 | Semiconductor device including a stacked capacitor A stacked capacitor formed in a capacitor hole includes a bottom electrode, capacitor insulation film and a top electrode. The bottom electrode includes a plurality of islands formed on an underlying insulating film, and a metallic film covering the islands on the u... | 04/08/2008 |
| 7354822 | Method of forming a MOSFET with dual work function materials A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical p... | 04/08/2008 |
| 7339224 | Trench capacitor and corresponding method of production The invention relates to a trench capacitor, in particular for use in a semiconductor memory cell, comprising a trench (2), embodied in a substrate (1), a first region (1a), provided in the substrate (1), as first capacitor electro... | 03/04/2008 |
| 7335554 | Method for fabricating semiconductor A method for fabricating a semiconductor device includes forming a first trench by etching a substrate already provided with a storage node contact (SNC) region and a bit line contact (BLC) region, forming a protection layer on sidewalls of the first trench, forming... | 02/26/2008 |
| 7332390 | Semiconductor memory device and fabrication thereof A semiconductor memory device and fabrication method thereof. In a semiconductor memory device, each memory cell comprises a deep trench and a capacitor disposed on the lower portion thereof. A collar oxide layer having a first second sidewalls is disposed on the de... | 02/19/2008 |
| 7316951 | Fabrication method for a trench capacitor having an insulation collar The present invention provides a fabrication method for a trench capacitor having an insulation collar (10) in a silicon substrate (1), having the steps of: providing a trench (5) in the silicon substrate (1); providing the insulation col... | 01/08/2008 |
| 7312114 | Manufacturing method for a trench capacitor having an isolation collar electrically connected with a substrate on a single side via a buried contact for use in a semiconductor memory cell The present invention relates to a manufacturing method for a trench capacitor having an isolation collar which is electrically connected with a substrate on a single side via a buried contact. More specifically, the present invention relates to manufacturing method... | 12/25/2007 |
| 7291533 | Method for production of trench DRAM cells and a trench DRAM cell array with fin field-effect transistors with a curved channel (CFET—curved fets) A method for producing trench DRAM cells, each having a trench capacitor and a fin field-effect transistor with a curved channel (CFET) for addressing the trench capacitor, is described. The memory cells are arranged in cell rows offset with respect to one another a... | 11/06/2007 |
| 7271083 | One-transistor random access memory technology compatible with metal gate process One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric... | 09/18/2007 |
| 7271052 | Long retention time single transistor vertical memory gain cell A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the higher band gap energy of silicon carbide as compared to silicon. The silicon carbide provides much lowe... | 09/18/2007 |
| 7250336 | Method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure The present invention provides a method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure, comprising the steps of: providing a trench in the microelectronic or micromechanical structure; providing a partial filling in the t... | 07/31/2007 |
| 7229877 | Trench capacitor with hybrid surface orientation substrate Methods of forming a deep trench capacitor memory device and logic devices on a single chip with hybrid surface orientation. The methods allow for fabrication of a system-on-chip (SoC) with enhanced performance including n-type complementary metal oxide semiconducto... | 06/12/2007 |
| 7158399 | Digital data apparatuses and digital data operational methods Digital data apparatuses and digital data operational methods are described. According to one embodiment, a digital data apparatus includes a semiconductive substrate comprising a node location configured to receive an electrical charge of a single bit of digital in... | 01/02/2007 |
| 7157329 | Trench capacitor with buried strap A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a plan... | 01/02/2007 |
| 7144770 | Memory cell and method for fabricating it The invention provides a method for fabricating a memory cell, a substrate (101) being provided, a trench-type depression (102) being etched into the substrate (101), a barrier layer (103) being deposited non-conformally in the trench-typ... | 12/05/2006 |
| 7109543 | Semiconductor device having trench capacitor and method for fabricating the same A semiconductor device and a method for fabricating the same. The device comprises a silicon substrate having a conductive well; a trench formed in the conductive well; a plate electrode formed on the sidewall of the trench; a capacitor insulating film and a storage... | 09/19/2006 |
| 7078289 | Method for fabricating a deep trench capacitor of DRAM device A method for fabricating a deep trench capacitor of DRAM devices is disclosed. A substrate with a deep trench formed therein is provided. The trench is then doped to form a buried plate electrode serving as a first electrode of the deep trench capacitor at a lower p... | 07/18/2006 |
| 7071054 | Methods of fabricating MIM capacitors in semiconductor devices Methods of fabricating an MIM capacitor and a dual damascene structure of a semiconductor device are disclosed. According to one example, a method includes depositing a first insulating layer on a semiconductor substrate; forming a lower interconnect through the fir... | 07/04/2006 |
| 6703311 | Method for estimating capacitance of deep trench capacitors A method for estimating capacitance of deep trench capacitor in a substrate. After a photoresist layer used to define the region of the lower electrode is formed on an oxide layer doping with a conducting type dopant, the height difference of the photores... | 03/09/2004 |
| 6703315 | Method of providing a shallow trench in a deep-trench device A method of forming a shallow trench within a trench capacitor structure. This method can be used, for example, in the construction of a DRAM device. The method comprises: (1) providing a trench capacitor structure comprising (a) a silicon substrate havin... | 03/09/2004 |
| 6699747 | Method for increasing the capacitance in a storage trench In a method for forming a trench capacitor a first layer of silicon oxide is deposited in a storage trench and a layer of silicon is deposited over the first layer by a chemical vapor deposition process. A layer of an oxidizable metal is deposited over th... | 03/02/2004 |
| 6699794 | Self aligned buried plate A method of forming a buried plate in a silicon substrate uses a silicon substrate having a deep trench etched into the silicon substrate. A highly doped polysilicon layer is formed within the trench. A nitride layer is then formed within the trench over ... | 03/02/2004 |
| 6693016 | Method of fabricating a trench-structure capacitor device The novel trench capacitors have a constant or increased capacitance. Materials for a second electrode region and if appropriate a first electrode region include a metallic material, a metal nitride, or the like, and/or a dielectric region is formed with ... | 02/17/2004 |
| 6686617 | Semiconductor chip having both compact memory and high performance logic A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory regi... | 02/03/2004 |
| 6674113 | Trench capacitor and method for manufacturing the same A trench capacitor has a first capacitor electrode, a second capacitor electrode, and a dielectric, which is arranged between the capacitor electrodes. The first capacitor electrode has a tube-like structure, which extends into a substrate. The second cap... | 01/06/2004 |
| 6670234 | Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof A method for fabricating DRAM and flash memory cells on a single chip includes providing a silicon substrate, forming a trench capacitor for each of the DRAM cells in the silicon substrate, forming isolation regions in the silicon substrate which are elec... | 12/30/2003 |
| 6670665 | Memory module with improved electrical properties A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of the memory cell array, which dummy memory cells are not used for storing items of information. F... | 12/30/2003 |
| 6670235 | Process flow for two-step collar in DRAM preparation In a method of forming a DRAM cell in a semiconductor substrate, the improvement of maintaining a substantially full trench opening during trench processing comprising: a) forming a pad nitride on the surface of the substrate and reactive ion etching (RIE... | 12/30/2003 |
| 6664167 | Memory with trench capacitor and selection transistor and method for fabricating it A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least ... | 12/16/2003 |
| 6664161 | Method and structure for salicide trench capacitor plate electrode The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is... | 12/16/2003 |
| 6661050 | Memory cell structure with trench capacitor and method for fabrication thereof Within both a memory cell structure and a method for fabricating the memory cell structure there is employed a storage capacitor formed within a trench adjoining an active region of a semiconductor substrate. Within the memory cell structure and the metho... | 12/09/2003 |
| 6661049 | Microelectronic capacitor structure embedded within microelectronic isolation region Within a method for fabricating a capacitor structure, and a capacitor structure fabricated employing the method, there is formed within an isolation region adjoining an active region of a semiconductor substrate a laterally asymmetric trench which leaves... | 12/09/2003 |
| 6649996 | In situ and ex situ hardmask process for STI with oxide collar application A method or process for etching a trench in an IC structure is disclosed. The IC structure might be comprised of a plurality of different component materials arranged proximate to one another, all of which need to be etched down to a target level. A first... | 11/18/2003 |
| 6639264 | Method and structure for surface state passivation to improve yield and reliability of integrated circuit structures A method for passivating surface states in an integrated circuit structure having a gate conductor with a gate dielectric layer. The method comprises the step of fabricating a solid state source of fluorine in close proximity to the gate dielectric layer.... | 10/28/2003 |
| 6638814 | Method for producing an insulation A method for producing a semiconductor device having a first region with storage capacitors and a second region with at least one well surrounded by an insulation. The method creates both the storage capacitors and the insulation by forming trenches in th... | 10/28/2003 |
| 6635543 | SOI hybrid structure with selective epitaxial growth of silicon A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad lay... | 10/21/2003 |
