Class 257/E21.648 - Capacitor stacked over transfer transis tor (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.647. This subclass
No. of patents: 1340
Last issue date: 10/21/2008

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Number	Title	Issue Date
6696716	Structures and methods for enhancing capacitors in integrated ciruits Systems, devices, structures, and methods are described that inhibit dielectric degradation in the presence of contaminants. An enhanced capacitor in a dynamic random access memory cell is discussed. The enhanced capacitor includes a first electrode, a di...	02/24/2004
6693015	Method for improved processing and etchback of a container capacitor A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor ...	02/17/2004
6686246	Method of fabricating a DRAM transistor with a dual gate oxide technique The process comprises the steps of growing a first oxide layer on the upper surface of a substrate; depositing a silicon nitride layer on top of the first oxide layer; patterning the silicon nitride layer with a photoresist mask to define field oxide area...	02/03/2004
6682984	Method of making a concave capacitor The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor t...	01/27/2004
6680502	Buried digit spacer separated capacitor array The present invention relates to the field of semiconductor integrated circuits and, in particular, to capacitor arrays formed over the bit line of an integrated circuit substrate. The present invention provides a method for forming stacked capacitors, in...	01/20/2004
6674169	Semiconductor device with titanium silicon oxide layer A semiconductor device comprised of a substantially conformal layer of titanium silicon oxide deposited on a semiconductor substrate. The layer of titanium silicon oxide is substantially free of chlorine related impurities. The layer of titanium silicon o...	01/06/2004
6673671	Semiconductor device, and method of manufacturing the same There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the...	01/06/2004
6670662	Semiconductor storage component with storage cells, logic areas and filling structures The invention provides a semiconductor memory component with random access, also having a structure which is differentiated into memory cells and logic regions and has a lower oxide layer arranged on a silicon substrate and an upper oxide layer arranged o...	12/30/2003
6670663	DRAM cell capacitor and manufacturing method thereof A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact b...	12/30/2003
6670256	Metal oxynitride capacitor barrier layer Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor ...	12/30/2003
6667502	Structurally-stabilized capacitors and method of making of same Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, which...	12/23/2003
6667208	Method for manufacturing a capacitor lower electrode over a transistor and a bit line corresponding to a cell area of a semiconductor device Disclosed is method for manufacturing a semiconductor device, wherein a photosensitive layer and a natural oxidation layer on a cell area and a peripheral circuit area are removed by dry etching while a capacitor of a DRAM device is manufactured, and a po...	12/23/2003
6664584	Metal oxynitride capacitor barrier layer Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor ...	12/16/2003
6665207	ROM embedded DRAM with dielectric removal/short A ROM embedded DRAM allows hard programming of ROM cells by shorting DRAM capacitor plates during fabrication. In one embodiment, the intermediate dielectric layer is removed and the plates are shorted with a conductor. In another embodiment, an upper con...	12/16/2003
6664583	Metal oxynitride capacitor barrier layer Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor ...	12/16/2003
6660536	Method of making ferroelectric material utilizing anneal in an electrical field A ferroelectric thin film precursor material is annealed while in an electric field. The electric field is maintained as the material cools. A partially completed integrated circuit with a ferroelectric thin film precursor material may be placed between t...	12/09/2003
6656781	METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, HAVING FIRST AND SECOND SEMICONDUCTOR REGIONS WITH FIELD SHIELD ISOLATION STRUCTURES AND A FIELD OXIDE FILM COVERING A JUNCTION BETWEEN SEMICONDUCTOR REGIONS A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover th...	12/02/2003
6656786	MIM process for logic-based embedded RAM having front end manufacturing operation A method and system for manufacturing an MIM capacitor for utilization with a logic-based embedded DRAM device. At least one transistor, an interlayer dielectric, at least one contact and at least one metal one layer are generally formed on a substrate du...	12/02/2003
6654295	Reduced topography DRAM cell fabricated using a modified logic process and method for operating same A memory system that includes a DRAM cell that includes an access transistor and a storage capacitor. The storage capacitor is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate...	11/25/2003
6653187	Semiconductor processing methods In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed ...	11/25/2003
6649956	Semiconductor integrated circuit device and manufacturing method thereof An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends ...	11/18/2003
6649469	Methods of forming capacitors A carbon containing masking layer is patterned to include a plurality of container openings therein having minimum feature dimensions of less than or equal to 0.20 micron. The container openings respectively have at least three peripheral corner areas whi...	11/18/2003
6645845	Methods of forming interconnect regions of integrated circuitry In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier lay...	11/11/2003
6645807	Method for manufacturing semiconductor device After a metal layer is formed on a dielectric film, the metal layer is subjected to an oxidation process using a liquid having oxidizing power, thereby forming an adhesion layer. Then, an electrode or wiring is formed on the adhesion layer....	11/11/2003
6642098	DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolat...	11/04/2003
6642564	Semiconductor memory and method for fabricating the same In a memory cell of a DRAM, that is, a semiconductor memory, a bit line connected to a bit line plug and a local interconnect are provided on a first interlayer insulating film. A connection conductor film of TiAlN is provided on the top and side faces of...	11/04/2003
6635933	Structure of a capacitor section of a dynamic random-access memory Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or th...	10/21/2003
6635310	Method of heat treatment A thermal processing method of the invention includes; a loading step of loading an object to be processed into a processing container, the object having a surface provided with a silicon film having a minutely irregular profile; and a doping step of intr...	10/21/2003
6635547	DRAM capacitor formulation using a double-sided electrode A capacitor having a double sided electrode for enhanced capacitance. In one embodiment, the double sided electrode capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The double sided electrode is preferably formed ...	10/21/2003
6635538	Method of manufacturing a semiconductor device When sidewalls (10) are formed by anisotropic etching, an insulating film (9) serves as a protective film for a major surface of a semiconductor substrate (100) and therefore prevents the major surface from suffering etching damage. That relieves an elect...	10/21/2003
6631069	Metal oxynitride capacitor barrier layer Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor ...	10/07/2003
6630378	Method of fabricating a dynamic random access memory device having stacked capacitor memory cell arrays A method of forming stacked capacitors over first field effect transistors having been provided in a memory cell area of a semiconductor memory device and at least a second field effect transistor in a peripheral circuit area of the semiconductor memory d...	10/07/2003
6627941	Capacitor for semiconductor device and method for manufacturing the same A capacitor for a semiconductor device is disclosed with increased capacitance which is produced by a simplified manufacturing process. The capacitor has a storage node electrode structure formed on the semiconductor device having impurity regions formed ...	09/30/2003
6627496	Process for producing structured layers, process for producing components of an integrated circuit, and process for producing a memory configuration A process for producing structured layers on a base body, in particular a semiconductor body, includes the steps of providing a first layer, structuring the first layer with a partial or complete local layer erosion to form raised and recessed layer regio...	09/30/2003
6627939	Semiconductor device provided with a capacitor having a high-permittivity insulator film In a disclosed semiconductor device, a capacitor includes a lower electrode consisting essentially of titanium nitride, a first capacity insulator film consisting of a tantalum oxide film formed on the lower electrode, a second capacity insulator film con...	09/30/2003
6627551	Method for avoiding microscratch in interlevel dielectric layer chemical mechanical polishing process This invention discloses a method for avoiding microscratch in interlevel dielectric layer chemical mechanical polishing process. There is step height difference on surface of the interlevel dielectric layer between the memory array and the logic device, ...	09/30/2003
6624018	Method of fabricating a DRAM device featuring alternate fin type capacitor structures A process for fabricating an alternate fin type capacitor structure, used to increase capacitor surface area has been developed. The process features the formation of fin shaped, storage node structures, located in fin type capacitor openings, which are i...	09/23/2003
6624021	Method for forming gate segments for an integrated circuit A method for forming gate segments in an integrated circuit. The method begins by forming a shallow trench isolation region outwardly from a layer of semiconductor material to isolate a plurality of active regions of the integrated circuit. After the isol...	09/23/2003
6624020	Fabrication method of semiconductor device with capacitor In a fabrication method of semiconductor device, a storage node connected to one of source/drain regions of an MOS (Metal Oxide Semiconductor) transistor provided at a semiconductor substrate is formed along a trench provided through a silicon nitride fil...	09/23/2003
6620680	Method of forming a contact structure and a container capacitor structure Method for forming at least a portion of a top electrode of a container capacitor and at least a portion of a contact plug in one deposition are described. In one embodiment, the top electrode is formed interior to a bottom electrode of the container capa...	09/16/2003

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Class 257/E21.648 - Capacitor stacked over transfer transis tor (EPO)