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| Number | Title | Issue Date |
| 7439132 | Semiconductor device comprising capacitor and method of fabricating the same A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. ... | 10/21/2008 |
| 7439118 | Method of manufacturing semiconductor integrated circuit A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETs, and the memory array part having N-type and P-type FETs, includes the steps of forming N-type and P-type FETs c... | 10/21/2008 |
| 7425724 | Memory device and method of production and method of use of same and semiconductor device and method of production of same A memory device able to be produced without requiring high precision alignment, a method of production of the same, and a method of use of a memory device produced in this way, wherein a peripheral circuit portion (first semiconductor portion) formed by a first mini... | 09/16/2008 |
| 7422943 | Semiconductor device capacitors with oxide-nitride layers and methods of fabricating such capacitors Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is o... | 09/09/2008 |
| 7420238 | Semiconductor constructions The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conduc... | 09/02/2008 |
| 7411237 | Lanthanum hafnium oxide dielectrics Dielectric layers containing a lanthanum hafnium oxide layer, where the lanthanum hafnium oxide layer is arranged as a structure of one or more monolayers, provide an insulating layer in a variety of structures for use in a wide range of electronic devices. ... | 08/12/2008 |
| 7408215 | Dynamic random access memory A DRAM structure on a silicon substrate has an active area, gate conductors, deep trench capacitors, and vertical transistors. The deep trench capacitors are formed at intersections of the active area and the gate conductors, and each deep trench capacitor is couple... | 08/05/2008 |
| 7402489 | Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same A storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode including a barrier layer interposed between a conductive plug and an oxidation resistant layer. A layer of titanium silicide is fabricated to lie between th... | 07/22/2008 |
| 7402487 | Process for fabricating a semiconductor device having deep trench structures A process for fabricating a semiconductor device having deep trench structures includes forming a first portion of the trench in a semiconductor substrate and a second portion of the trench in a selectively-formed upper layer. After etching the substrate to form the... | 07/22/2008 |
| 7385235 | Spacer chalcogenide memory device The present invention includes devices and methods to form memory cell devices including a spacer comprising a programmable resistive material alloy. Particular aspects of the present invention are described in the claims, specification and drawings. ... | 06/10/2008 |
| 7384841 | DRAM device and method of manufacturing the same In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a... | 06/10/2008 |
| 7378704 | Semiconductor constructions, and methods of forming semiconductor constructions The invention includes methods of incorporating partial SOI into transistor structures. In particular aspects, dielectric material is provided over semiconductor material, and patterned into at least two segments separated by a gap. Additional semiconductor material... | 05/27/2008 |
| 7368752 | DRAM memory cell A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/... | 05/06/2008 |
| 7368776 | Semiconductor device comprising a highly-reliable, constant capacitance capacitor A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. ... | 05/06/2008 |
| 7368352 | Semiconductor devices having transistors with vertical channels and method of fabricating the same In a semiconductor device and a method of fabricating the same, a vertical channel transistor has a cell occupation area of 4F2. The semiconductor device comprises: a cell array region having a plurality of unit cells, each unit cell having a cell occupat... | 05/06/2008 |
| 7364966 | Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then f... | 04/29/2008 |
| 7361545 | Field effect transistor with buried gate pattern A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film,... | 04/22/2008 |
| 7361974 | Manufacturing method for an integrated semiconductor structure The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a... | 04/22/2008 |
| 7361549 | Method for fabricating memory cells for a memory device The invention provides a method for fabricating a memory device having memory cells which are formed on a microstructured driving unit (100), in which method a shaping layer (104) is provided and is patterned in such a manner that vertical trench struc... | 04/22/2008 |
| 7348620 | Forming phase change memories Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the... | 03/25/2008 |
| 7348234 | Methods of forming capacitor constructions The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a si... | 03/25/2008 |
| 7342272 | Flash memory with recessed floating gate A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substr... | 03/11/2008 |
| 7341904 | Capacitorless 1-transistor DRAM cell and fabrication method A semiconductor device is fabricated by forming a trench in a semiconductor body. A region of dielectric material is formed within at least a lower portion of the trench. An upper portion of the semiconductor body is doped. A cutout is formed in the semiconductor ma... | 03/11/2008 |
| 7341909 | Methods of forming semiconductor constructions The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. ... | 03/11/2008 |
| 7339222 | Method for determining wordline critical dimension in a memory array and related structure According to one exemplary embodiment, a method for fabricating a memory array includes forming a number of trenches in a substrate, where the trenches determine a number of wordline regions in the substrate, where each of the wordline regions is situated between tw... | 03/04/2008 |
| 7335554 | Method for fabricating semiconductor A method for fabricating a semiconductor device includes forming a first trench by etching a substrate already provided with a storage node contact (SNC) region and a bit line contact (BLC) region, forming a protection layer on sidewalls of the first trench, forming... | 02/26/2008 |
| 7332418 | High-density single transistor vertical memory gain cell A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away f... | 02/19/2008 |
| 7326985 | Method for fabricating metallic bit-line contacts A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between th... | 02/05/2008 |
| 7326614 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby A method of forming an array of floating gate memory cells, and an array formed thereby, that includes source and drain regions formed in a substrate, and a conductive block of material disposed over the source region. The floating gate is formed as a thin, L-shaped... | 02/05/2008 |
| 7323739 | Semiconductor device having recess and planarized layers A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a ... | 01/29/2008 |
| 7316961 | Method of manufacturing semiconductor device Provided is a method of manufacturing a semiconductor device with enhancements of electrical characteristics. The method includes sequentially forming a lower electrode and an insulating layer on a semiconductor substrate, dry-etching a region of the insulating laye... | 01/08/2008 |
| 7314798 | Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the tr... | 01/01/2008 |
| 7303971 | MSM binary switch memory device A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over... | 12/04/2007 |
| 7285468 | Methods of forming semiconductor constructions The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. Th... | 10/23/2007 |
| 7276753 | Dynamic random access memory cell and fabricating method thereof A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided. The patterned mask layer exposes the deep trench. A deep trench capacitor is formed inside the deep tren... | 10/02/2007 |
| 7262053 | Terraced film stack A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack,... | 08/28/2007 |
| 7262095 | System and method for reducing process-induced charging A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate. ... | 08/28/2007 |
| 7262452 | Method of forming DRAM device having capacitor and DRAM device so formed In a method of forming a DRAM device having a capacitor and a DRAM device so formed, an interlayer dielectric having at least one layer is formed on a semiconductor substrate. The interlayer dielectric layer and a predetermined portion of the semiconductor substrate... | 08/28/2007 |
| 7259065 | Method of forming trench in semiconductor device There are provided a method of forming a trench for a recessed channel of a transistor and a layout for the same. A layout for the recessed channel according to one aspect of the present invention is formed such that an open region is extended across at least one of... | 08/21/2007 |
| 7259076 | High-density SOI cross-point memory fabricating method A method for fabricating a high-density silicon-on-insulator (SOI) cross-point memory array and an array structure are provided. The method includes the following steps: selectively forming a hard mask on an SOI substrate, defining memory areas, active device areas,... | 08/21/2007 |
