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| Number | Title | Issue Date |
| 7439117 | Method for designing a micro electromechanical device with reduced self-actuation A method is described for designing a micro electromechanical device in which the risk of self-actuation of the device in use is reduced. The method includes locating a first conductor in a plane and locating a second conductor with its collapsible portion at a pred... | 10/21/2008 |
| 7439118 | Method of manufacturing semiconductor integrated circuit A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETs, and the memory array part having N-type and P-type FETs, includes the steps of forming N-type and P-type FETs c... | 10/21/2008 |
| 7432150 | Method of manufacturing a magnetoelectronic device A method of manufacturing a magnetoelectronic device includes providing an electrically conducting material and an electrically insulating material adjacent to at least a portion of the electrically conducting material, and implanting a magnetic material into the el... | 10/07/2008 |
| 7416942 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device is provided. The method includes successively forming a first silicon film and a mask film above a semiconductor substrate through a gate insulating film, forming a plurality of trenches in the first silicon film and... | 08/26/2008 |
| 7416945 | Method for forming a split gate memory device A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial ... | 08/26/2008 |
| 7414283 | Semiconductor device A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which ... | 08/19/2008 |
| 7407897 | Capacitor of analog semiconductor device having multi-layer dielectric film and method of manufacturing the same In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage ... | 08/05/2008 |
| 7402499 | Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widt... | 07/22/2008 |
| 7396723 | Method of manufacturing EEPROM device A method of manufacturing an EEPROM device can reduce the cell area. The method of manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) includes forming a mask pattern over a semiconductor substrate; forming a gate oxide layer over a top of ... | 07/08/2008 |
| 7393736 | Atomic layer deposition of ZrHfSnOfilms as high k gate dielectrics The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO2), hafnium oxide (HfO2) and tin oxide (SnO2) acting as a single dielectric layer with a formula of ZrXHfYSn... | 07/01/2008 |
| 7384841 | DRAM device and method of manufacturing the same In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a... | 06/10/2008 |
| 7378341 | Automatic process control of after-etch-inspection critical dimension Automatic process control of after-etch-inspection critical dimension. A dielectric layer is deposited over a substrate and is then planarized to a first thickness. A cap oxide layer having a second thickness is deposited, wherein the combination of the first thickn... | 05/27/2008 |
| 7368352 | Semiconductor devices having transistors with vertical channels and method of fabricating the same In a semiconductor device and a method of fabricating the same, a vertical channel transistor has a cell occupation area of 4F2. The semiconductor device comprises: a cell array region having a plurality of unit cells, each unit cell having a cell occupat... | 05/06/2008 |
| 7361974 | Manufacturing method for an integrated semiconductor structure The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a... | 04/22/2008 |
| 7358140 | Pattern density control using edge printing processes A structure fabrication method. The method comprises providing a design structure that includes (i) a design substrate and (ii) M design normal regions on the design substrate, wherein M is a positive integer greater than 1. Next, N design sacrificial regions are ad... | 04/15/2008 |
| 7335940 | Flash memory and manufacturing method thereof A method for manufacturing flash memory is provided. A tunneling dielectric layer, a conductive layer and a patterned mask layer that exposes a portion of the conductive layer are formed on a substrate. An oxide layer is formed on the exposed conductive layer so tha... | 02/26/2008 |
| 7332377 | Manufacturing method with self-aligned arrangement of solid body electrolyte memory cells of minimum structure size The object of providing a method for manufacturing solid body electrolyte memory cells or CB memory cells, respectively, which is suited for the simplified manufacturing of highly dense arrays with crosspoint architecture is solved by the present invention in that t... | 02/19/2008 |
| 7332378 | Integrated circuit memory system with dummy active region An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming s... | 02/19/2008 |
| 7323739 | Semiconductor device having recess and planarized layers A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a ... | 01/29/2008 |
| 7314803 | Method for producing a semiconductor structure In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of g... | 01/01/2008 |
| 7303971 | MSM binary switch memory device A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over... | 12/04/2007 |
| 7271063 | Method of forming FLASH cell array having reduced word line pitch A method of forming a NAND Flash memory device includes forming a control gate polysilicon layer over a substrate, forming a mask layer over the control gate polysilicon layer, the mask layer including a mask pattern defining a plurality of spaced word lines of the ... | 09/18/2007 |
| 7265381 | Opto-electronic memory element on the basis of organic metalloporphyrin molecules A memory cell for opto-electronic applications includes a substrate, a first electrode and a second electrode, and an active layer arranged between the first and the second electrodes, wherein the active layer includes a metalloporphyrin derivative, and wherein the ... | 09/04/2007 |
| 7259067 | Method for manufacturing flash memory device The present invention relates to a method for manufacturing a flash memory device. A plurality of conductive layers and dielectric layers are etched in a single etch apparatus, thus forming a control gate and a floating gate. In a gate formation process in which a t... | 08/21/2007 |
| 7208371 | Method of fabricating split gate flash memory device A method of fabricating a split gate flash memory device by which stringer generation is prevented. The method includes forming a dielectric layer on an active area of a semiconductor substrate, forming a first gate covered with a cap layer on the dielectric layer, ... | 04/24/2007 |
| 7081389 | Semiconductor devices having dual capping layer patterns and methods of manufacturing the same Some embodiments provide a semiconductor substrate having a cell array region and a peripheral circuit region. A plurality of word line patterns are placed in the cell array region, each of which include a word line and a word line capping layer pattern stacked ther... | 07/25/2006 |
| 6700165 | Semiconductor structure with the common source line A semiconductor structure with common source line, the semiconductor structure has two word lines, some bit lines, a silicon-based layer and a suicide layer. The silicon-based layer is located between and electrically separated from these word lines, but ... | 03/02/2004 |
| 6696351 | Semiconductor device having a selectively deposited conductive layer A process of production of a semiconductor memory device having a memory array including memory cells and a peripheral circuit on one substrate comprising the process of forming an interlayer insulating layer covering the memory array and peripheral circu... | 02/24/2004 |
| 6696339 | Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices The present invention is directed toward methods of fabricating components for microelectronic devices, microelectronic devices including memory cells or other components, and computers including memory devices. For example, one embodiment is directed tow... | 02/24/2004 |
| 6683353 | Semiconductor integrated circuit device In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated ... | 01/27/2004 |
| 6683342 | Memory structure and method for manufacturing the same A memory structure and the method for fabricating the same are disclosed in this present invention. A first gate structure and a second gate structure are provided onto a substrate. After an implanting process, the first gate structure will become the per... | 01/27/2004 |
| 6677199 | Structure for preventing salicide bridging and method thereof A semiconductor device having a memory array that includes a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, wherein each of the plurality of the word lines is substantially perpendicular to each of the plu... | 01/13/2004 |
| 6670234 | Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof A method for fabricating DRAM and flash memory cells on a single chip includes providing a silicon substrate, forming a trench capacitor for each of the DRAM cells in the silicon substrate, forming isolation regions in the silicon substrate which are elec... | 12/30/2003 |
| 6667524 | Semiconductor device with a plurality of semiconductor elements A first semiconductor element is a transistor for use in a memory cell region, and a second semiconductor element is a transistor for use in a peripheral circuit region. A first total impurity concentration of a first impurity diffusion region and a secon... | 12/23/2003 |
| 6664586 | Memory device and manufacturing method thereof The invention provides a memory device including a memory substrate, an insulating layer, a shielding metal layer, a second dielectric layer and a second metal layer. The memory substrate includes a substrate, a memory cell area, a peripheral circuit area... | 12/16/2003 |
| 6653187 | Semiconductor processing methods In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed ... | 11/25/2003 |
| 6653684 | Integrated circuit including high-voltage and logic transistors and EPROM cells An integrated circuit including logic MOS transistors, EPROM cells, and high-voltage MOS transistors. Each EPROM cell includes a floating gate formed from a first polysilicon level above a tunnel oxide and a control gate formed from a second polysilicon l... | 11/25/2003 |
| 6642093 | Method for manufacturing a semiconductor device According to the present invention, a method for manufacturing a semiconductor device forms a cobalt silicide film 11 on source/drain regions 7a and 7b and a gate electrode 4 of transistors in the logic circuit region, making it possible to form a high-pe... | 11/04/2003 |
| 6642111 | Memory device structure and method of fabricating the same A method of fabricating a memory device structure, where the method includes the steps of forming a tunnel oxide layer, a silicon nitride layer and a silicon oxide layer. A conductive layer is then formed on top of the silicon oxide. The conductive layer ... | 11/04/2003 |
| 6627928 | Method of manufacturing an integrated circuit, for integrating an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the sem... | 09/30/2003 |
