Class 257/E21.644 - With particular manufacturing method of wells or tubs, e.g., twin tubs, high energy well implants, buried implanted layers for lateral isolation (BILLI) (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.616. This subclass
No. of patents: 240
Last issue date: 10/21/2008

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Number	Title	Issue Date
7439140	Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within...	10/21/2008
7361549	Method for fabricating memory cells for a memory device The invention provides a method for fabricating a memory device having memory cells which are formed on a microstructured driving unit (100), in which method a shaping layer (104) is provided and is patterned in such a manner that vertical trench struc...	04/22/2008
7361540	Method of reducing noise disturbing a signal in an electronic device Certain aspects of a method for reducing noise disturbing at least one signal in an electronic device may comprise shielding a first layer doped with a first dopant from a signaling layer employing a second layer doped with a second dopant. A first signaling compone...	04/22/2008
7354833	Method for improving threshold voltage stability of a MOS device This invention provides a method for improving threshold voltage stability of at least one metal-oxide-semiconductor (MOS) device. In one embodiment of the invention, at least one well is formed on a semiconductor substrate. A gate dielectric layer is formed on the ...	04/08/2008
7297590	Method for fabricating an integrated pin diode and associated circuit arrangement A method for producing an integrated PIN photodiode. The PIN photodiode contains a doped region of a first conduction type near the substrate and a doped region that is remote from the substrate. The doped region that is remote from the substrate has a different con...	11/20/2007
7294564	Method for forming a layered semiconductor technology structure and corresponding layered semiconductor technology structure The following invention provides a method for forming a layered semiconductor structure having a layer of a first semiconductor material on a substrate of at least one second semiconductor material, comprising the steps of: providing said substrate; burying said lay...	11/13/2007
7282402	Method of making a dual strained channel semiconductor device According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. ...	10/16/2007
7273776	Methods of forming a P-well in an integrated circuit device The present invention is generally directed to a method of forming a p-well in an integrated circuit device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial material above an active layer of a substrate, forming a first doped ...	09/25/2007
7223664	Semiconductor device and method for fabricating the same The semiconductor device comprises gate electrodes 50 formed on a silicon substrate 32 with a gate insulation film 48 formed therebetween, source/drain diffused layers 66n, 66p formed in the silicon substrate 32	05/29/2007
7208367	Methods of fabricating ferroelectric memory devices having expanded plate lines A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferr...	04/24/2007
6946339	Method for creating a stepped structure on a substrate In a method for creating a stepped structure on a substrate, which at least includes a first portion with a first thickness and a second portion with a second thickness, at first a layer sequence of a first oxide layer, a first nitride layer, and a second oxide laye...	09/20/2005
6703187	Method of forming a self-aligned twin well structure with a single mask An improved method for forming a self-aligned twin well structure for use in a CMOS semiconductor device including providing a substrate for forming a twin well structure therein; forming an implant masking layer over the substrate to include a process su...	03/09/2004
6699761	Method for fabricating y-direction, self-alignment mask ROM device A method for fabricating a y-direction, self-alignment mask ROM device is described. The method includes forming a buried drain region in a substrate and forming a gate oxide layer on the substrate. Perpendicular to the direction of the buried drain regio...	03/02/2004
6677194	Method of manufacturing a semiconductor integrated circuit device A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step...	01/13/2004
6667522	Silicon wafers for CMOS and other integrated circuits Techniques include heating a substantially uniformly boron-doped wafer to achieve a significantly increased resistivity in a near-surface region of the wafer and forming at least one electrical circuit element in the near-surface region. Integrated circui...	12/23/2003
6667205	Method of forming retrograde n-well and p-well A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shif...	12/23/2003
6664602	Semiconductor device and method of manufacturing the same An object of the invention is to suppress degradation of the effective isolation width between a well and a diffusion layer caused by impurity ion implantation for forming the well performed at a predetermined incident angle. A well is formed by performin...	12/16/2003
6664608	Back-biased MOS device A plurality of p-wells and n-wells are formed in a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side of the bulk material and the plurality of n-wells and p-wells. T...	12/16/2003
6660579	Zero power memory cell with improved data retention A method for forming a three transistor zero power memory cell including a p-channel sense transistor, an n-channel write transistor, and an n-channel sense transistor including: implanting a p-type impurity into a p-type substrate in which a n-channel hi...	12/09/2003
6656800	Method of manufacturing semiconductor device including process for implanting impurities into substrate via MOS transistor gate electrode and gate insulation film A gate oxide film and a first layer of a multi-layered gate electrode are stacked on a substrate and by a gate prefabrication technique, an oxide layer of an element isolation region is formed in a self-alignment manner using the first layer of the gate e...	12/02/2003
6645854	Formation of a vertical junction throuph process simulation based optimization of implant doses and energies A substantially vertical isolation junction between semiconductor devices is provided. The substantially vertical junction between a P-doped region and an N-doped region allows the P-doped region to be adjacent to the N-doped region with a lateral stagger...	11/11/2003
6647542	Efficient fabrication process for dual well type structures An efficient method for fabricating dual well type structures uses the same number of masks used in single well type structure fabrication. In a preferred embodiment, the current invention allows low voltage and high voltage n-channel transistors and low ...	11/11/2003
6642562	CMOS type solid imaging device A solid imaging device including: a semiconductor substrate of a first conductivity type; a layer of a second conductivity type formed on a surface of the semiconductor substrate, the layer at least including a photosensitive portion of the second conduct...	11/04/2003
6638804	Method of manufacturing semiconductor device with high and low breakdown transistors Among first and second oxide films 110 and 112 formed on a substrate 100, the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left inta...	10/28/2003
6627937	Semiconductor memory device The present invention contemplates a highly reliable semiconductor memory device. The semiconductor memory device includes a silicon substrate containing a p impurity of a first concentration, an epitaxial layer formed at the silicon substrate and contain...	09/30/2003
6617218	Manufacturing method for semiconductor device A region around the gate of a PMOSFET that does not, at a minimum, affect the transistor characteristics is covered with a resist and a diagonal ion implantation for drain engineering is carried out in a P well region beneath gate electrode. Ions of a fir...	09/09/2003
6617217	Reduction in well implant channeling and resulting latchup characteristics in shallow trench isolation by implanting wells through nitride Retrograde wells are formed by implanting through nitride films (40). Nitride films (40) are formed after STI (20) formation. By selectively masking a portion of the wafer with photoresist (47) after portions of a retrograde well are formed (45, 50, 55, a...	09/09/2003
6610585	Method for forming a retrograde implant A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant...	08/26/2003
6605872	Method for fabricating a semiconductor device including a latch-up preventing conductive layer Provided with a semiconductor device which is adopted to reduce the resistance of a well without the need to increase the concentration of dopants in forming the well by depositing conductive layer patterns and then growing an epitaxial layer on the condu...	08/12/2003
6599804	Fabrication of field-effect transistor for alleviating short-channel effects Short-channel threshold voltage roll-off and punchthrough in an IGFET (40 or 42) having a channel zone (64 or 84) situated in body material (50) are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a loc...	07/29/2003
6586296	Method of doping wells, channels, and gates of dual gate CMOS technology with reduced number of masks A method is provided for processing a semiconductor topography. In particular, a method is provided for forming wells of opposite conductivity type using a single patterned layer. In addition, the method may include forming a silicon layer having first an...	07/01/2003
6583001	Method for introducing an equivalent RC circuit in a MOS device using resistive paths A method for providing low power MOS devices that include resistive paths specifically designed to provide a specified resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is in...	06/24/2003
6583486	Semiconductor memory device and its method of manufacture A semiconductor memory device comprises a semiconductor substrate having a memory cell region and a periphery circuit region. The memory cell region includes first and second conductivity type wells and an array of memory cell formed on the first and seco...	06/24/2003
6573577	Semiconductor device and method for fabricating the same A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the d...	06/03/2003
6548383	Twin well methods of forming CMOS integrated circuitry In accordance with an aspect of the invention, a twin-well method of forming CMOS integrated circuitry having first and second conductivity type gates includes conducting a first conductivity type well implant, a second conductivity type well implant, a f...	04/15/2003
6548842	Field-effect transistor for alleviating short-channel effects An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local su...	04/15/2003
6535034	High performance integrated circuit devices adaptable to use lower supply voltages with smaller device geometries A high performance integrated circuit device enables scaled low voltage transistors to be utilized as transfer gates with improved speed characteristics. At least some of the transistors are formed with thicker gate oxides and boosted positive and negativ...	03/18/2003
6531356	Semiconductor devices and methods of manufacturing the same Embodiments include a semiconductor device including a well structure such that well areas can be formed with a higher density of integration and a plurality of high-voltage endurable transistors can be driven independently of one another with different v...	03/11/2003
6509250	Method for CMOS well drive in a non-inert ambient Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomp...	01/21/2003
6489224	Method for engineering the threshold voltage of a device using buried wells Buried platform wells are specifically used to electrically interact with the platform transistors of the invention. The dopant concentration distribution of the buried platform wells is used to change the threshold voltage of the platform transistors of ...	12/03/2002

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Class 257/E21.644 - With particular manufacturing method of wells or tubs, e.g., twin tubs, high energy well implants, buried implanted layers for lateral isolation (BILLI) (EPO)