Did You Know...
...that the Eveready Battery began as an invention called the "electric flowerpot," which was a tube with a battery and light bulb inside? The idea was to fasten this gizmo to the side of a flowerpot so it would illuminate the flowers from the bottom. The idea died on the vine and the businessman who licensed the flower pot, Conrad Huber, was left with a pile of useless tubes -- until he found a way to market them as batteries to light the world!
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| Number | Title | Issue Date |
| 7432134 | Semiconductor device and method of fabricating the same A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 forme... | 10/07/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7329916 | DRAM cell arrangement with vertical MOS transistors The invention is related to a DRAM cell arrangement with vertical MOS transistors. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors bel... | 02/12/2008 |
| 7288815 | Semiconductor device and manufacturing method thereof A semiconductor device (20, 21, 22), including: a channel region (4) of a first conductivity type formed at a surface layer portion of a semiconductor substrate (1); a source region (25) of a second conductivity type which is different fr... | 10/30/2007 |
| 7282402 | Method of making a dual strained channel semiconductor device According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. ... | 10/16/2007 |
| 7271048 | Method for manufacturing trench MOSFET A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is f... | 09/18/2007 |
| 7229872 | Low voltage power MOSFET device and process for its manufacture A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capaci... | 06/12/2007 |
| 6674099 | MISFET A metal insulator semiconductor field effect transistor (MISFET) is disclosed comprising a source layer being made with a material having a source band-gap (EG2) and a source mid-gap value (EGM2), the source layer having a source Fermi-Level (EF2). A drai... | 01/06/2004 |
| 6670694 | Semiconductor device A surface orientation other than a (100) surface orientation is exposed to the surface portion of a silicon substrate having the (100) surface orientation, for example. A silicon epitaxial growth layer is formed only on a region containing a channel formi... | 12/30/2003 |
| 6653181 | CMOS integrated circuit having vertical transistors and a process for fabricating same A process for fabricating a CMOS integrated circuit with vertical MOSFET devices is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer... | 11/25/2003 |
| 6632712 | Method of fabricating variable length vertical transistors A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the comp... | 10/14/2003 |
| 6610575 | Forming dual gate oxide thickness on vertical transistors by ion implantation A method of structures having dual gate oxide thicknesses, comprising the following steps. A substrate having first and second pillars is provided. The first and second pillars each having an outer side wall and an inner side wall. At least one of the out... | 08/26/2003 |
| 6580154 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the direction. Advantageously, improvements in hole carrier mobility ... | 06/17/2003 |
| 6566202 | Integrated circuit having at least two vertical MOS transistors and method for manufacturing same An integrated circuit having at least two vertical MOS transistors, and method for manufacturing same, wherein first source/drain regions of the two vertical MOS transistors are located in an upper region of sidewalls of a trench. A second source/drain re... | 05/20/2003 |
| 6518112 | High performance, low power vertical integrated CMOS devices A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETs; logic gates including at least one vertical FET or at least one multi-d... | 02/11/2003 |
| 6503784 | Double gated transistor A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, ... | 01/07/2003 |
| 6496034 | Programmable logic arrays with ultra thin body transistors Structures and methods for programmable logic arrays are provided. In one embodiment, the programmable logic array includes a first logic plane and a second logic plane. The first logic plane receives a number of input signals. The first logic plane has a... | 12/17/2002 |
| 6492232 | Method of manufacturing vertical semiconductor device An n-channel device (10) and a p-channel device (11) are formed from a single epitaxial silicon layer (60,61). During the deposition of the single epitaxial silicon layer (60,61), dopants are added to the epitaxial reaction chamber and subsequently change... | 12/10/2002 |
| 6483171 | Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form ... | 11/19/2002 |
| 6461900 | Method to form a self-aligned CMOS inverter using vertical device integration A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprises silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon laye... | 10/08/2002 |
| 6459123 | Double gated transistor A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, ... | 10/01/2002 |
| 6391698 | Forming complementary metal-oxide semiconductor with gradient doped source/drain The present invention provides a method for forming a transistor with a gradient doped source/drain. The method comprises the following steps. First, two first N-wells are formed in a substrate and the first N-wells are separated in both sides of the subs... | 05/21/2002 |
| 6376313 | Integrated circuit having at least two vertical MOS transistors and method for manufacturing same An integrated circuit having at least two vertical MOS transistors, and method for manufacturing same, wherein first source/drain regions of the two vertical MOS transistors are located in an upper region of sidewalls of a trench. A second source/drain re... | 04/23/2002 |
| 6372559 | Method for self-aligned vertical double-gate MOSFET A method of forming a self-aligned vertical double-gate metal oxide semiconductor field effect transistor (MOSFET) device is provided that includes processing steps that are CMOS compatible. The method include the steps of growing an oxide layer on a surf... | 04/16/2002 |
| 6344381 | Method for forming pillar CMOS A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the ... | 02/05/2002 |
| 6297531 | High performance, low power vertical integrated CMOS devices A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETS; logic gates including at least one vertical FET or at least one multi-d... | 10/02/2001 |
| 6255699 | Pillar CMOS structure A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the ... | 07/03/2001 |
| 6245615 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the direction. Advantageously, improvements in hole carrier mobility ... | 06/12/2001 |
| 6207977 | Vertical MISFET devices The present invention relates to processes for fabrication of Vertical MISFET devices or a stack of several of such devices. The Vertical MISFET device comprises a highly doped drain region, a non or lowly doped channel region and a source region forming ... | 03/27/2001 |
| 6127230 | Vertical semiconductor device and method of manufacturing the same An n-channel device (10) and a p-channel device (11) are formed from a single epitaxial silicon layer (60,61). During the deposition of the single epitaxial silicon layer (60,61), dopants are added to the epitaxial reaction chamber and subsequently change... | 10/03/2000 |
| 6107663 | Circuit and method for gate-body structures in CMOS technology A circuit and method for an improved inverter is provided. The present invention capitalizes on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. Additionally, the gate and body of ... | 08/22/2000 |
| 6100123 | Pillar CMOS structure A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in th... | 08/08/2000 |
| 6060911 | Circuit arrangement with at least four transistors, and method for the manufacture thereof In the circuit arrangement two of the four vertical transistors are complementary to the remaining two transistors. Two of the transistors are respectively arranged at the same level. For this purpose, layer structures (St1, St2, St3, St4) are structured ... | 05/09/2000 |
| 6060754 | Circuit and method for gate-body structures in CMOS technology A circuit and method for an improved inverter is provided. The present invention capitalizes on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. Additionally, the gate and body of ... | 05/09/2000 |
| 6048776 | Semiconductor device and a method of fabricating the same A method of fabricating a semiconductor device, comprises the steps of forming a trench in a semiconductor substrate by using a selective etching process; forming an insulating layer at least on the inner surface of the trench; forming a film containing s... | 04/11/2000 |
| 6013545 | Method of manufacturing high-voltage metal-oxide-semiconductor device A method of manufacturing a high-voltage metal-oxide-semiconductor device that uses trenches instead of a field oxide layer as an isolating structure, and employs a vertical layout rather than a horizontal layout so that more area is available for forming... | 01/11/2000 |
| 5963800 | CMOS integration process having vertical channel The present invention relates to processes for fabrictation of Vertical MISFET devices or a stack of several Vertical MISFET devices having high fabrication yield.... | 10/05/1999 |
| 5925909 | Three-dimensional complementary field effect transistor process and structures A field effect transistor has a short gate and is fabricated by: doping the bottom surface of a depression to form a relatively lightly doped region in the bottom of the depression; forming the gate of the field effect transistor on the sidewall of the de... | 07/20/1999 |
| 5920088 | Vertical MISFET devices The present invention relates to Silicon Germanium-based Vertical MISFET devices allowing smaller device size and exhibiting significant advantages over prior devices related to the reduction of drain induced barrier lowering and parasitic capacitance and... | 07/06/1999 |
| 5914504 | DRAM applications using vertical MISFET devices The present invention relates to RAM circuits comprising memory cells and logic circuitry wherein each of the memory cells comprise at least one Vertical MISFET device comprising a stack of several layers a source layer, a channel layer, a drain layer and... | 06/22/1999 |
