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| Number | Title | Issue Date |
| 7425489 | Self-aligned shallow trench isolation A method of making a semiconductor structure includes etching an isolation oxide. The isolation oxide is in a substrate, a gate layer is on the substrate, a patterned metallic layer is on the gate layer, and a first patterned etch-stop layer is on the metallic layer... | 09/16/2008 |
| 7422947 | Semiconductor device and method of manufacturing the same A semiconductor device manufacturing method comprises depositing a semiconductor layer and mask material in order over a semiconductor substrate on an insulating film; patterning the semiconductor layer and mask material to form a semiconductor layer in a predetermi... | 09/09/2008 |
| 7410840 | Building fully-depleted and bulk transistors on same chip A method (10) of forming fully-depleted silicon-on-insulator (FD-SOI) transistors (150) and bulk transistors (152) on a semiconductor substrate (104) as part of an integrated circuit fabrication process is disclosed. ... | 08/12/2008 |
| 7361540 | Method of reducing noise disturbing a signal in an electronic device Certain aspects of a method for reducing noise disturbing at least one signal in an electronic device may comprise shielding a first layer doped with a first dopant from a signaling layer employing a second layer doped with a second dopant. A first signaling compone... | 04/22/2008 |
| 7282402 | Method of making a dual strained channel semiconductor device According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. ... | 10/16/2007 |
| 7045410 | Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI) A method (200) of forming an isolation structure is disclosed, and includes forming a patterned isolation hard mask layer (206, 212) having an isolation opening associated therewith over a semiconductor body. An implant into the isolation opening is th... | 05/16/2006 |
| 6703271 | Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The compos... | 03/09/2004 |
| 6703187 | Method of forming a self-aligned twin well structure with a single mask An improved method for forming a self-aligned twin well structure for use in a CMOS semiconductor device including providing a substrate for forming a twin well structure therein; forming an implant masking layer over the substrate to include a process su... | 03/09/2004 |
| 6686252 | Method and structure to reduce CMOS inter-well leakage A method of forming a semiconductor device with improved leakage control, includes: providing a semiconductor substrate; forming a trench in the substrate; forming a leakage stop implant in the substrate under the bottom of the trench and under and aligne... | 02/03/2004 |
| 6670681 | Semiconductor structures A method of implanting dopants into a semiconductor structure wherein a lateral periphery of a photoresist mask is shifted after implanting a first dopant and prior to implanting a second dopant. The invention also includes semiconductor structures having... | 12/30/2003 |
| 6670680 | Semiconductor device comprising a dual gate CMOS A dual gate type CMOS device according to the present invention includes a silicon substrate having a trench in the main surface and a gate electrode including a polysilicon film and a tungsten silicide film formed above the main surface via a gate insula... | 12/30/2003 |
| 6667522 | Silicon wafers for CMOS and other integrated circuits Techniques include heating a substantially uniformly boron-doped wafer to achieve a significantly increased resistivity in a near-surface region of the wafer and forming at least one electrical circuit element in the near-surface region. Integrated circui... | 12/23/2003 |
| 6667205 | Method of forming retrograde n-well and p-well A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shif... | 12/23/2003 |
| 6664602 | Semiconductor device and method of manufacturing the same An object of the invention is to suppress degradation of the effective isolation width between a well and a diffusion layer caused by impurity ion implantation for forming the well performed at a predetermined incident angle. A well is formed by performin... | 12/16/2003 |
| 6664608 | Back-biased MOS device A plurality of p-wells and n-wells are formed in a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side of the bulk material and the plurality of n-wells and p-wells. T... | 12/16/2003 |
| 6656781 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, HAVING FIRST AND SECOND SEMICONDUCTOR REGIONS WITH FIELD SHIELD ISOLATION STRUCTURES AND A FIELD OXIDE FILM COVERING A JUNCTION BETWEEN SEMICONDUCTOR REGIONS A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover th... | 12/02/2003 |
| 6649461 | Method of angle implant to improve transistor reverse narrow width effect A new angle implant is provided that reduces or eliminates the effects of narrow channel impurity diffusion to surrounding regions of insulation. The invention provides for angle implantation of p-type impurities into corners of STI regions that are adjac... | 11/18/2003 |
| 6645854 | Formation of a vertical junction throuph process simulation based optimization of implant doses and energies A substantially vertical isolation junction between semiconductor devices is provided. The substantially vertical junction between a P-doped region and an N-doped region allows the P-doped region to be adjacent to the N-doped region with a lateral stagger... | 11/11/2003 |
| 6642112 | Non-oxidizing spacer densification method for manufacturing semiconductor devices Non-oxidizing spacer densification method for producing semiconductor devices, such as MOSFET devices, and that may be implemented during semiconductor fabrication with little or substantially no polycide adhesion loss experienced during spacer densificat... | 11/04/2003 |
| 6638844 | Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semiconductor technology by backside trench and fill A method of reducing substrate coupling and noise for one or more RFCMOS components comprising the following steps. A substrate having a frontside and a backside is provided. One or more RFCMOS components are formed over the substrate. One or more isolati... | 10/28/2003 |
| 6630710 | Elevated channel MOSFET The present invention provides a semiconductor device (e.g., MOSFET) having a channel above the surface of the wafer containing a well and a junction. The elevated channel may be selectively epitaxially grown and enables higher mobility, thereby enabling ... | 10/07/2003 |
| 6624043 | Metal gate CMOS and method of manufacturing the same A metal gate complementary metal oxide semiconductor (CMOS) and a method of manufacturing the same is disclosed. The method includes depositing the metal gate electrode material as a final step before metallization of the device. Accordingly, the metal ga... | 09/23/2003 |
| 6617217 | Reduction in well implant channeling and resulting latchup characteristics in shallow trench isolation by implanting wells through nitride Retrograde wells are formed by implanting through nitride films (40). Nitride films (40) are formed after STI (20) formation. By selectively masking a portion of the wafer with photoresist (47) after portions of a retrograde well are formed (45, 50, 55, a... | 09/09/2003 |
| 6614078 | Highly latchup-immune CMOS I/O structures CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n... | 09/02/2003 |
| 6613635 | Method of fabricating semiconductor device having element isolation trench Threshold voltage fluctuation in upper corner portions of a trench isolation is inhibited by rounding upper corner portions of the trench by thermal oxidation, introducing a first impurity into both upper corner portions of the trench and heat-treating th... | 09/02/2003 |
| 6610585 | Method for forming a retrograde implant A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant... | 08/26/2003 |
| 6600186 | Process technology architecture of embedded DRAM Embedded DRAM cells within an ASIC having a pass transistor with a gate oxide having a thickness equal to the thickness of the gate oxide of the logic core. This allows the embedded DRAM cell to be activated by signals having voltage levels equal to the v... | 07/29/2003 |
| 6583011 | Method for forming damascene dual gate for improved oxide uniformity and control A method to grow layers of gate oxide or gate base materials of different thicknesses for dual gate structures. The process starts with a semiconductor surface in which STI regions have been formed and over the surface of which a layer of gate base materi... | 06/24/2003 |
| 6583000 | Process integration of Si1-xGex CMOS with Si1-xGex relaxation after STI formation A method of forming a CMOS device includes preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about... | 06/24/2003 |
| 6583060 | Dual depth trench isolation A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structu... | 06/24/2003 |
| 6583001 | Method for introducing an equivalent RC circuit in a MOS device using resistive paths A method for providing low power MOS devices that include resistive paths specifically designed to provide a specified resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is in... | 06/24/2003 |
| 6563181 | High frequency signal isolation in a semiconductor device A semiconductor device (20) includes an isolated p-well (22) formed in a substrate (21) by a buried n-well (25) and an n-well ring (24). The n-well ring (24) extends from a surface of the semiconductor device (20) to the buried n-well (25). The isolated p... | 05/13/2003 |
| 6552400 | Semiconductor device and method of manufacturing the same Disclosed herein is a semiconductor device wherein element active regions for an N channel region and a P channel region are formed so as to adjoin each other, and gate electrode is formed so as to stride over both channel regions and an element isolation... | 04/22/2003 |
| 6544829 | Polysilicon gate salicidation A method of fabricating a substantially completely silicided polysilicon gate electrode in a CMOS process flow. A hard mask material is formed on an integrated circuit substrate, where the integrated circuit substrate includes an unpatterned polysilicon l... | 04/08/2003 |
| 6531356 | Semiconductor devices and methods of manufacturing the same Embodiments include a semiconductor device including a well structure such that well areas can be formed with a higher density of integration and a plurality of high-voltage endurable transistors can be driven independently of one another with different v... | 03/11/2003 |
| 6528855 | MOSFET having a low aspect ratio between the gate and the source/drain A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitanc... | 03/04/2003 |
| 6525394 | Substrate isolation for analog/digital IC chips The specification describes techniques for isolating noisy subcircuits in integrated analog/digital devices. Isolation is obtained using a modification of triple well isolation wherein the deep isolation implant is restricted to the digital circuits only ... | 02/25/2003 |
| 6524916 | Controlled gate length and gate profile semiconductor device and manufacturing method therefor An ultra-large scale integrated circuit semiconductor device is provided which has inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrie... | 02/25/2003 |
| 6521953 | Semiconductor CMOS structures with an undoped region A method of implanting dopants into a semiconductor structure is described wherein a lateral periphery of a photoresist mask is shifted after implanting a first dopant and prior to implanting a second dopant. Also semiconductor structures having two doped... | 02/18/2003 |
| 6518155 | Device structure and method for reducing silicide encroachment A semiconductor device having a novel spacer structure and method of fabrication. The present invention describes a semiconductor device which has an electrode with a first thickness. A silicide layer having a second thickness is formed on the electrode. ... | 02/11/2003 |
