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| Number | Title | Issue Date |
| 7420280 | Reduced stress under bump metallization structure An improved under bump structure for use in semiconductor devices is described. The under bump structure includes a passivation layer having a plurality of vias. The vias are positioned such that a plurality of vias are associated with (i.e., located over) each cont... | 09/02/2008 |
| 7413975 | Interconnect substrate, semiconductor device, methods of manufacturing the same, circuit board, and electronic equipment A first conductive layer is formed. An insulating layer is formed so that at least a part of the insulating layer is disposed on the first conductive layer. A second conductive layer is formed so that at least a part of the second conductive layer is disposed on the... | 08/19/2008 |
| 7397073 | Barrier dielectric stack for seam protection The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal ... | 07/08/2008 |
| 7374992 | Manufacturing method for an integrated semiconductor structure The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device ... | 05/20/2008 |
| 7368321 | Semiconductor package and method for manufacturing the same A semiconductor package includes: a first substrate including: a semiconductor base material having a first side and a second side; a functional element that is provided at the first side of the semiconductor base material; a first wiring; a pad that is electrically... | 05/06/2008 |
| 7338871 | Method for fabricating semiconductor device The present invention provides a method for fabricating a semiconductor device capable of preventing a contact resistance from increasing in a region contacted to an N-type conductive region during forming a conductive pattern directly contacted to the N-type conduc... | 03/04/2008 |
| 7339204 | Backside contact for touchchip A contact is formed within an active region of a substrate at the edge of a die, preferably within the first metallization level in the active region of the substrate. An opening having sloped sidewalls is then etched into the back side of the substrate, exposing a ... | 03/04/2008 |
| 7320934 | Method of forming a contact in a flash memory device A method of forming a contact between a bitline and a local interconnect in a flash memory device comprises forming a hard mask layer on a planarized surface that includes an exposed top section of the local interconnects prior to depositing an oxide dielectric laye... | 01/22/2008 |
| 7300862 | Method for manufacturing semiconductor device High quality dielectric layers may be achieved without introducing excessive impurities when a semiconductor device is manufactured by a method that includes forming a lower wire layer on a structure above a semiconductor substrate, forming a silicon rich oxide laye... | 11/27/2007 |
| 7282402 | Method of making a dual strained channel semiconductor device According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. ... | 10/16/2007 |
| 7271086 | Microfeature workpieces and methods of forming a redistribution layer on microfeature workpieces Methods for forming a redistribution layer on microfeature workpieces, and microfeature workpieces having such a redistribution layer are disclosed herein. In one embodiment, a method includes constructing a dielectric structure on a microfeature workpiece having a ... | 09/18/2007 |
| 7262120 | Method for fabricating metal line in semiconductor device A method for fabricating a metal line in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer on a substrate; forming a contact hole by etching the inter-layer insulation layer; forming a metal layer on the inter-layer ins... | 08/28/2007 |
| 7247947 | Semiconductor device comprising a plurality of semiconductor constructs A semiconductor device includes a first semiconductor construct provided on a base plate and having a semiconductor substrate and external connection electrodes. An insulating layer is provided on the base plate around the first semiconductor construct. An upper lay... | 07/24/2007 |
| 7247562 | Semiconductor element, semiconductor device and methods for manufacturing thereof The present invention provides a method of manufacturing a semiconductor element having a miniaturized structure and a semiconductor device in which the semiconductor element having a miniaturized structure is integrated highly, by overcoming reduction of the yield ... | 07/24/2007 |
| 7238606 | Semiconductor devices and method for fabricating the same Methods for fabricating a copper interconnect of a semiconductor device are disclosed. An example method for fabricating a copper interconnect of a semiconductor device deposits a first insulating layer on a substrate having at least one predetermined structure, for... | 07/03/2007 |
| 7202158 | Method for fabricating a metal-insulator-metal capacitor A method fabricating multiple wiring metals in a semiconductor device. The method includes forming a lower wiring metal on a semiconductor substrate, forming an interlayer dielectric on the lower wiring metal, and selectively removing the interlayer dielectric to fo... | 04/10/2007 |
| 7202163 | Local interconnection method and structure for use in semiconductor device A Local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local in... | 04/10/2007 |
| 7192859 | Method of manufacturing semiconductor device and display device To provide a method of forming a wiring for the purpose of providing a semiconductor device, which is superior in reliability and cost performance. Further, to provide methods of manufacturing a semiconductor device and a display device by using the method of formin... | 03/20/2007 |
| 7186639 | Metal interconnection lines of semiconductor devices and methods of forming the same Metal interconnection lines of semiconductor devices and methods of forming the same are disclosed. Improved reliability is achieved in a disclosed metal line of a semiconductor device by preventing metal layers from eroding and preventing metal lines from being des... | 03/06/2007 |
| 7180192 | Semiconductor device A semiconductor device includes an insulating film whose relative dielectric constant is 3.4 or less, at least one conductive layer, at least one conductive plug which is electrically connected to the conductive layer to form a conduction path, at least one reinforc... | 02/20/2007 |
| 7176056 | Semiconductor integrated circuit device and method of manufacturing the same Arrangements are provided to effectively prevent wire disconnection generated due to an increase of heat applied to a semiconductor integrated circuit device The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is p... | 02/13/2007 |
| 7157372 | Coaxial through chip connection A method performed on a wafer having multiple chips, each including a doped semiconductor and substrate, involves etching an annulus trench partially into the substrate, metalizing the annulus trench with a metal, etching a via trench within the periphery of the ann... | 01/02/2007 |
| 7030918 | Solid-state image pickup device The present invention discloses a solid-state image pickup device in which a photoelectric conversion part having a photoelectric conversion region, and a logic circuit part are formed on a semiconductor substrate, and outputs a potential change caused by the charge... | 04/18/2006 |
| 6700163 | Selective silicide blocking A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has suicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area a... | 03/02/2004 |
| 6696327 | Method for making a semiconductor device having a high-k gate dielectric A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, then forming a capping layer on the high-k gate dielectric layer. After oxidizing the capping layer to form a capping die... | 02/24/2004 |
| 6670680 | Semiconductor device comprising a dual gate CMOS A dual gate type CMOS device according to the present invention includes a silicon substrate having a trench in the main surface and a gate electrode including a polysilicon film and a tungsten silicide film formed above the main surface via a gate insula... | 12/30/2003 |
| 6653690 | Semiconductor device comprising high density integrated circuit having a large number of insulated gate field effect transistors It is a purpose of the invention to provide a semiconductor device comprising a high density integrated circuit having a large number of insulated gate field effect transistors having minute size and improved performance and uniformity. The source contact... | 11/25/2003 |
| 6635522 | Method of forming a MOS transistor in a semiconductor device and a MOS transistor fabricated thereby Methods of forming a MOS transistor and a MOS transistor fabricated thereby are provided. The MOS transistor includes a semiconductor substrate of a first conductivity type, and an insulated gate pattern having sidewalls disposed on a predetermined region... | 10/21/2003 |
| 6632716 | Semiconductor device and manufacturing method thereof A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a g... | 10/14/2003 |
| 6611009 | Cross-coupled transistor pair A cross-coupled transistor pair includes separately arranged first and second active areas. A gate area of a first transistor is arranged symmetrically on portions of the first and second active areas. A gate area of a second transistor is also arranged s... | 08/26/2003 |
| 6602746 | Dual-gate CMOS semiconductor device manufacturing method A manufacturing method for a dual-gate CMOS semiconductor device that suppresses mutual diffusion of P type impurities and N type impurities in a gate electrode. An NMOS part and a PMOS part are formed on a semiconductor substrate. A polycrystalline silic... | 08/05/2003 |
| 6600198 | Electrostatic discharge protection circuit for a semiconductor device A semiconductor device having high ESD resistance includes an internal circuit, an I/O pad, a division circuit connected to a lead-in line connecting the internal circuit and the I/O pad for outputting an electric signal from first and second terminals co... | 07/29/2003 |
| 6593631 | Method of fabricating semiconductor device A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and secon... | 07/15/2003 |
| 6586305 | Method for producing transistors in integrated semiconductor circuits Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel area by changing the ionization energy (work function) of the electrons. Transistors in semicond... | 07/01/2003 |
| 6583052 | Method of fabricating a semiconductor device having reduced contact resistance A method of fabricating a semiconductor device having the steps of forming an isolation layer in a silicon substrate to define an active region and a device isolation region; forming a junction region in the active region of the silicon substrate; forming... | 06/24/2003 |
| 6570231 | Semiconductor device with varying width electrode An n-channel active region, a p-channel active region and an isolation insulating film are formed, and a silicon film is deposited via a gate insulating film. After introducing n-type impurities into the n-channel region and p-type impurities into the p-c... | 05/27/2003 |
| 6569729 | Method of fabricating three dimensional CMOSFET devices for an embedded DRAM application A method of reducing the aspect ratio for dry etch processes used to form contact hole and storage node openings in composite insulator layers, to expose regions of CMOS devices used for embedded memory cell applications, has been developed. The method fe... | 05/27/2003 |
| 6552400 | Semiconductor device and method of manufacturing the same Disclosed herein is a semiconductor device wherein element active regions for an N channel region and a P channel region are formed so as to adjoin each other, and gate electrode is formed so as to stride over both channel regions and an element isolation... | 04/22/2003 |
| 6544888 | Advanced contact integration scheme for deep-sub-150 nm devices An advanced contact integration technique for deep-sub-150 nm semiconductor devices such as W/WN gate electrodes, dual work function gates, dual gate MOSFETs and SOI devices. This technique integrates self-aligned raised source/drain contact processes wit... | 04/08/2003 |
| 6512278 | Stacked semiconductor integrated circuit device having an inter-electrode barrier to silicide formation The present invention provides a semiconductor integrated circuit having excellent junction characteristics when applying the silicide technology to an extremely narrowed diffusion layer between adjacent gate electrodes as well as a method for manufacturi... | 01/28/2003 |
