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| Number | Title | Issue Date |
| 7435683 | Apparatus and method for selectively recessing spacers on multi-gate devices Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed. ... | 10/14/2008 |
| 7432120 | Method for realizing a hosting structure of nanometric elements Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side wall. Depositing on at least one portion of sad surface and on the b... | 10/07/2008 |
| 7419865 | Methods of forming memory circuitry The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sac... | 09/02/2008 |
| 7399690 | Methods of fabricating semiconductor devices and structures thereof Methods of forming spacers on sidewalls of features of semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece and at least one feature disposed over the workpiece. A first spacer is d... | 07/15/2008 |
| 7381623 | Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second ga... | 06/03/2008 |
| 7378308 | CMOS devices with improved gap-filling A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the ... | 05/27/2008 |
| 7358128 | Method for manufacturing a transistor A semiconductor device and a method for manufacturing the same is disclosed, in which a spacer containing nitrogen therein has a tensile stress and enables device reliability improvement by improving the On-current without regard to the kind of transistor. The semic... | 04/15/2008 |
| 7354839 | Gate structure and a transistor having asymmetric spacer elements and methods of forming the same Methods for forming asymmetric gate structures comprising spacer elements disposed on the opposed sides of a gate electrode and having a different width are disclosed. The asymmetric gate structures are employed to form an asymmetric design of a halo region and exte... | 04/08/2008 |
| 7344984 | Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwante... | 03/18/2008 |
| 7314793 | Technique for controlling mechanical stress in a channel region by spacer removal During the formation of a transistor element, sidewalls spacers are removed or at least partially etched back after ion implantation and silicidation, thereby rendering the mechanical coupling of a contact etch stop layer to the underlying drain and source regions m... | 01/01/2008 |
| 7306996 | Methods of fabricating a semiconductor device having a metal gate pattern A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer st... | 12/11/2007 |
| 7297584 | Methods of fabricating semiconductor devices having a dual stress liner In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, an... | 11/20/2007 |
| 7291895 | Integrated circuitry A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the s... | 11/06/2007 |
| 7282402 | Method of making a dual strained channel semiconductor device According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. ... | 10/16/2007 |
| 7271049 | Method of forming self-aligned low-k gate cap A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be signi... | 09/18/2007 |
| 7271455 | Formation of fully silicided metal gate using dual self-aligned silicide process An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of for... | 09/18/2007 |
| 7268393 | Semiconductor devices and methods of manufacturing the same Semiconductor devices and methods of manufacturing semiconductor devices which achieve higher integration and higher operating speed are provided. A disclosed example semiconductor device includes a semiconductor substrate of a first conductivity type; a gate insula... | 09/11/2007 |
| 7256464 | Metal oxide semiconductor transistor and fabrication method thereof A metal oxide semiconductor transistor comprising a first doping type substrate, an isolation layer, a plurality of gates, a masking layer, a gate oxide layer, a plurality of second doping type source/drain regions and spacers. The first doping type substrate has a ... | 08/14/2007 |
| 7247917 | Nonvolatile semiconductor memory devices and methods of manufacturing the same Nonvolatile semiconductor memory devices and methods of manufacturing the same are disclosed. A disclosed nonvolatile semiconductor memory cell includes a semiconductor substrate; first and second semiconductor cells positioned on the semiconductor substrate at a di... | 07/24/2007 |
| 7235447 | Fabrication method for a semiconductor structure and corresponding semiconductor structure The present invention provides a fabrication method for a semiconductor structure and a corresponding semiconductor structure. The fabrication method comprises the following steps: provision of a semiconductor substrate (1) with a gate dielectric (5... | 06/26/2007 |
| 7230296 | Self-aligned low-k gate cap A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be signi... | 06/12/2007 |
| 7223647 | Method for forming integrated advanced semiconductor device using sacrificial stress layer An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS tra... | 05/29/2007 |
| 7208361 | Replacement gate process for making a semiconductor device that includes a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a polysilicon layer on a dielectric layer, which is formed on a substrate. The polysilicon layer is etched to generate a patterned polysilicon layer with an upper surface that is ... | 04/24/2007 |
| 7189617 | Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the requi... | 03/13/2007 |
| 7176125 | Method of forming a static random access memory with a buried local interconnect An SRAM cell includes six transistors. The storage nodes are implemented using local interconnects. A first level of metal overlies the interconnects but is electrically isolated therefrom. Contact plugs are formed to couple the cell to the first level of metal. The... | 02/13/2007 |
| 7148113 | Semiconductor device and fabricating method thereof A method for fabricating a semiconductor device is described. A gate dielectric layer is formed on a substrate, and several gate structures having a gate conductor, a cap layer and spacers are formed on the gate dielectric layer. A mask layer is formed over the subs... | 12/12/2006 |
| 7132342 | Method of reducing fringing capacitance in a MOSFET In a method of reducing the fringing capacitance of a MOSFET, the nitride spacers on the sides of the MOSFET gate are etched away to form trenches, which are plugged to define air spacers. ... | 11/07/2006 |
| 7132704 | Transistor sidewall spacer stress modulation A semiconductor fabrication process and the resulting integrated circuit include forming a gate electrode (116) over a gate dielectric (104) over a semiconductor substrate (102). A spacer film (124) exhibiting a tensile stress characteris... | 11/07/2006 |
| 7129127 | Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation A method (200) fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes (210) on a semiconductor body and active regions defined within the semiconductor body in PMOS and NMOS regions. A nitride containing cap ... | 10/31/2006 |
| 7098098 | Methods for transistors formation using selective gate implantation Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a... | 08/29/2006 |
| 7094636 | Method of forming a conductive line A method of forming a conductive line includes forming conductive material received over a semiconductor substrate into a line having opposing sidewalls. Insulative material is deposited over the line, and is planarized. An insulating spacer forming layer is deposit... | 08/22/2006 |
| 7091549 | Programmable memory devices supported by semiconductor substrates The invention includes a memory device supported by a semiconductor substrate and comprising in ascending order from the substrate: a floating gate, a dielectric material, a layer consisting essentially of tungsten nitride, a first mass consisting essentially of tun... | 08/15/2006 |
| 7078287 | Method of manufacturing semiconductor device A gate electrode is formed on a silicon substrate. First spacers are formed on side surfaces of the gate electrode. With the gate electrode and the first spacers as masks, the surface of the silicon substrate is chipped off to form steplike portions at positions adj... | 07/18/2006 |
| 6794764 | Charge-trapping memory arrays resistant to damage from contact hole information The present invention relates to a memory array comprising a substrate and a plurality of bitlines having contacts and a plurality of wordlines intersecting the bitlines. A protective spacer is used to separate the bitline contacts from the wordlines adjacent to the... | 09/21/2004 |
| 6699763 | Disposable spacer technology for reduced cost CMOS processing A method of fabricating a CMOS transistor using a silicon germanium disposable spacer (114) for the source/drain implant. After gate etch, silicon germanium disposable spacers (114) are formed. A NMOS resist pattern (116) is formed exposing the NMOS regio... | 03/02/2004 |
| 6696334 | Method for formation of a differential offset spacer A method for differential offset spacer formation suitable for incorporation into manufacturing processes for advanced CMOS-technologies devices is presented. The method comprises forming a first insulative layer overlying a plurality of gate structures, ... | 02/24/2004 |
| 6673665 | Semiconductor device having increased metal silicide portions and method of forming the semiconductor The surface area of silicon lines which receives a silicide portion is increased to decrease the line resistance in narrow polysilicon lines, such as gate electrodes. Sidewall spacers are formed such that an upper portion of the line sidewall is exposed s... | 01/06/2004 |
| 6667197 | Method for differential oxidation rate reduction for n-type and p-type materials A method of forming a substantially uniform oxide film over surfaces with different level of doping and/or different dopant type is disclosed. In one aspect, a method for forming a uniform oxide spacer on the sidewalls of heavily doped n- and p-type gates... | 12/23/2003 |
| 6667206 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device in which an increase in a parasitic resistance can be prevented, resulting in prevention of a deterioration in a current driving capability and a reduction in an operating speed of a semiconductor integrate... | 12/23/2003 |
| 6664173 | Hardmask gate patterning technique for all transistors using spacer gate approach for critical dimension control An electrical element may be made by providing a hardmask unit that has a double gate stack with a first gate layer, a first hardmask layer formed over the first gate layer, a second gate layer formed over the first hardmask layer, and a second hardmask l... | 12/16/2003 |
