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| Number | Title | Issue Date |
| 7361932 | Semiconductor device and method for fabricating the same A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a... | 04/22/2008 |
| 7355256 | MOS Devices with different gate lengths and different gate polysilicon grain sizes A semiconductor device 1 according to the present invention includes a semiconductor substrate 5, a first transistor 10 which is formed on the semiconductor substrate 5 and includes a first gate electrode portion 16 constituted by ... | 04/08/2008 |
| 7335542 | Semiconductor device with mushroom electrode and manufacture method thereof A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed ... | 02/26/2008 |
| 7332775 | Protruding spacers for self-aligned contacts A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous c... | 02/19/2008 |
| 7326609 | Semiconductor device and fabrication method A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is... | 02/05/2008 |
| 7285450 | Method of fabricating non-volatile memory A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell includes a first composite layer, a first gate and a cap layer. There is a gap between two adjacent ... | 10/23/2007 |
| 7282402 | Method of making a dual strained channel semiconductor device According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. ... | 10/16/2007 |
| 7223645 | Semiconductor device with mushroom electrode and manufacture method thereof A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed ... | 05/29/2007 |
| 7157378 | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on... | 01/02/2007 |
| 7144780 | Semiconductor device and its manufacturing method The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistor... | 12/05/2006 |
| 7091563 | Method and structure for improved MOSFETs using poly/silicide gate height control A method for manufacturing an integrated circuit that has a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor. This method involves depositing oxide fill on the n-type transistor and the p-type transi... | 08/15/2006 |
| 6855605 | Semiconductor device with selectable gate thickness and method of manufacturing such devices A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts... | 02/15/2005 |
| 6703670 | Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention ... | 03/09/2004 |
| 6682988 | Growth of photoresist layer in photolithographic process A method of fabricating a feature of an integrated circuit in a layer of material includes providing a layer of photoresist having a first thickness over the layer of material; forming apertures in the layer of photoresist; growing the layer of photoresis... | 01/27/2004 |
| 6674114 | Semiconductor device and manufacturing method thereof In a semiconductor device having P type and N type wells formed bordering on a step on a P type semiconductor substrate, a first transistor (precise transistor) having a first linewidth is formed on the P type well in a step lower region while a second tr... | 01/06/2004 |
| 6639287 | Semiconductor integrated circuit device A semiconductor device has a depletion type MIS transistor, a transistor forming a masked ROM, and a submicron CMOS integrated on a single or common semiconductor substrate, while minimizing the steps of manufacturing the depletion type MIS transistor. Du... | 10/28/2003 |
| 6638804 | Method of manufacturing semiconductor device with high and low breakdown transistors Among first and second oxide films 110 and 112 formed on a substrate 100, the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left inta... | 10/28/2003 |
| 6632731 | Structure and method of making a sub-micron MOS transistor A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second sel... | 10/14/2003 |
| 6633072 | Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the ... | 10/14/2003 |
| 6633070 | Semiconductor device A field-effect transistor including a gate electrode, silicon layers, and source and drain regions at a surface of a silicon substrate. Sidewall insulating films on the opposite side surfaces of the gate electrode are located between the gate electrode an... | 10/14/2003 |
| 6600198 | Electrostatic discharge protection circuit for a semiconductor device A semiconductor device having high ESD resistance includes an internal circuit, an I/O pad, a division circuit connected to a lead-in line connecting the internal circuit and the I/O pad for outputting an electric signal from first and second terminals co... | 07/29/2003 |
| 6580136 | Method for delineation of eDRAM support device notched gate A complementary metal oxide semiconductor integrated circuit containing a notched gate in the support device region as well as a method of forming the same are provided. The method of the present invention includes the steps of (a) forming a gate stack on... | 06/17/2003 |
| 6573577 | Semiconductor device and method for fabricating the same A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the d... | 06/03/2003 |
| 6541320 | Method to controllably form notched polysilicon gate structures A method and structure for forming a notched gate structure having a gate conductor layer on a gate dielectric layer. The gate conductor layer has a first thickness. The inventive method includes patterning a mask over the gate conductor layer, etching th... | 04/01/2003 |
| 6512258 | Semiconductor device and method of manufacturing same Provided are a semiconductor device that optimizes the operation characteristics such as of both an insulating gate type transistor for high voltage and an insulating gate type transistor for low voltage, and a method of manufacturing the same. Specifical... | 01/28/2003 |
| 6492212 | Variable threshold voltage double gated transistors and method of fabrication The present invention provides a double gate transistor and a method for forming the same that facilitates the formation of different transistors having different threshold voltages. The embodiments of the present invention form transistors having differe... | 12/10/2002 |
| 6486012 | Semiconductor device having field effect transistors different in thickness of gate electrodes and process of fabrication thereof An n-channel type field effect transistor and a p-channel type field effect transistor are fabricated on a p-type well and an n-type well, respectively, and the arsenic-doped gate electrode of the n-channel type field effect transistor is thinner than the... | 11/26/2002 |
| 6429066 | Method for producing a polysilicon circuit element A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the diel... | 08/06/2002 |
| 6420220 | Method of forming electrode for high performance semiconductor devices A method is provided for fabricating a semiconductor device, the method including forming a dielectric layer above a structure, forming a silicidable layer above the dielectric layer and forming a conductive layer above the silicidable layer. The method a... | 07/16/2002 |
| 6417086 | Method of manufacturing semiconductor device having nonvolatile memory and logic circuit using multi-layered, inorganic mask An inorganic film with a double-layers structure is used as an etching mask in an EEPROM area to pattern a double-layers gate, while a thin inorganic film obtained by removing one layer of the double-layers inorganic film by etching is used as an etching ... | 07/09/2002 |
| 6362038 | Low and high voltage CMOS devices and process for fabricating same CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a sin... | 03/26/2002 |
| 6355532 | Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET A short vertical channel, dual-gate, CMOS FET is fabricated by forming a plurality of channel segments in a starting material that extend longitudinally between source and drain areas. The channel segments are laterally separated from one another by space... | 03/12/2002 |
| 6355531 | Method for fabricating semiconductor devices with different properties using maskless process A method is provided for fabricating semiconductor devices having different properties on a common semiconductor substrate. The method includes the steps of (a) forming N openings on the semiconductor substrate, wherein each opening is corresponding to a ... | 03/12/2002 |
| 6350638 | Method of forming complementary type conductive regions on a substrate A method of forming complementary type conductive regions on a substrate includes, a) providing a first etch stop layer over a substrate; b) etching a void through the first etch stop layer inwardly towards the substrate; c) providing a first conductive l... | 02/26/2002 |
| 6287922 | Method for fabricating graded LDD transistor using controlled polysilicon gate profile An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer... | 09/11/2001 |
| 6274421 | Method of making metal gate sub-micron MOS transistor A MOS transistor is formed on a single crystal silicon substrate doped to form a conductive layer of a first type, and includes: an active region formed on said substrate; a source region and a drain region located in said active region, doped to form con... | 08/14/2001 |
| 6255704 | Semiconductor device and method for fabricating the same A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the d... | 07/03/2001 |
| 6232208 | Semiconductor device and method of manufacturing a semiconductor device having an improved gate electrode profile A semiconductor device is provided with a gate electrode having a substantially rectangular profile by depositing a layer of amorphous or microcrystalline silicon. The amorphous or microcrystalline silicon is doped with impurities, before patterning to fo... | 05/15/2001 |
| 6200842 | Method of forming complementary type conductive regions on a substrate A method of forming complementary type conductive regions on a substrate includes, a) providing a first etch stop layer over a substrate; b) etching a void through the first etch stop layer inwardly towards the substrate; c) providing a first conductive l... | 03/13/2001 |
| 6166413 | Semiconductor device having field effect transistors different in thickness of gate electrodes and process of fabrication thereof An n-channel type field effect transistor and a p-channel type field effect transistor are fabricated on a p-type well and an n-type well, respectively, and the arsenic-doped gate electrode of the n-channel type field effect transistor is thinner than the... | 12/26/2000 |
