Did You Know...
...that Robert Adler has the dubious distinction of being the Father of the Couch Potato? Back in 1955 Adler was employed by what was then Zenith Radio Corp., where he was charged to invent something that would allow viewers to turn down the TV volume without leaving their chairs. After a series of flops (such as a wired contraption that people tripped over), Adler hit on the idea of using sound waves. Thus the Remote Control was born...
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7432567 | Metal gate CMOS with at least a single gate metal and dual gate dielectrics A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single... | 10/07/2008 |
| 7432147 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device comprises: forming a device isolation, a first conductivity type region, and a second conductivity type region on a semiconductor substrate; depositing a gate insulating film on an entire surface of the semiconductor ... | 10/07/2008 |
| 7419867 | CMOS gate structure comprising predoped semiconductor gate material with improved uniformity of dopant distribution and method of forming the structure By predoping of a layer of deposited semiconductor gate material by incorporating dopants during the deposition process, a high uniformity of the dopant distribution may be achieved in the gate electrodes of CMOS devices subsequently formed in the layer of gate mate... | 09/02/2008 |
| 7390719 | Method of manufacturing a semiconductor device having a dual gate structure A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is... | 06/24/2008 |
| 7384830 | Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric fo... | 06/10/2008 |
| 7384851 | Buried stress isolation for high-performance CMOS technology A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of ... | 06/10/2008 |
| 7382023 | Fully depleted SOI multiple threshold voltage application An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A se... | 06/03/2008 |
| 7381619 | Dual work-function metal gates A semiconductor device having dual work-function structures, such as dual work-function gate electrodes of transistors. In the preferred embodiment in which NMOS and PMOS transistors are formed on a semiconductor device, the transistors are initially formed with a d... | 06/03/2008 |
| 7368796 | Metal gate engineering for surface P-channel devices A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix | 05/06/2008 |
| 7368372 | Methods of fabricating multiple sets of field effect transistors The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, t... | 05/06/2008 |
| 7361932 | Semiconductor device and method for fabricating the same A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a... | 04/22/2008 |
| 7355256 | MOS Devices with different gate lengths and different gate polysilicon grain sizes A semiconductor device 1 according to the present invention includes a semiconductor substrate 5, a first transistor 10 which is formed on the semiconductor substrate 5 and includes a first gate electrode portion 16 constituted by ... | 04/08/2008 |
| 7341916 | Self-aligned nanometer-level transistor defined without lithography A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates form... | 03/11/2008 |
| 7341900 | Semiconductor device and method for manufacturing the same A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and... | 03/11/2008 |
| 7332433 | Methods of modulating the work functions of film layers Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where t... | 02/19/2008 |
| 7314789 | Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. ... | 01/01/2008 |
| 7306996 | Methods of fabricating a semiconductor device having a metal gate pattern A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer st... | 12/11/2007 |
| 7297587 | Composite gate structure in an integrated circuit An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielec... | 11/20/2007 |
| 7297588 | Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities and a process for forming the same One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, ... | 11/20/2007 |
| 7282403 | Temperature stable metal nitride gate electrode An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is charact... | 10/16/2007 |
| 7282402 | Method of making a dual strained channel semiconductor device According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. ... | 10/16/2007 |
| 7262073 | CMOS image sensor and method of manufacturing same Disclosed are a complementary metal oxide semiconductor (CMOS) image sensor and a method of forming the same. The CMOS image sensor comprises a semiconductor substrate having a photodiode region and a transistor region. An optical path is formed between a micro lens... | 08/28/2007 |
| 7256084 | Composite stress spacer An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neu... | 08/14/2007 |
| 7253050 | Transistor device and method of manufacture thereof Methods of forming CMOS devices and structures thereof. A workpiece is provided having a first region and a second region. A high k gate dielectric material is formed over the workpiece. A first gate material comprising a first metal is formed over the high k gate d... | 08/07/2007 |
| 7253049 | Method for fabricating dual work function metal gates A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method ... | 08/07/2007 |
| 7229871 | Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. ... | 06/12/2007 |
| 7183168 | Method of manufacturing a semiconductor device having a silicide film A method of manufacturing a semiconductor device includes implanting germanium ions into a selected portion of a semiconductor region containing at least silicon, forming P-type and N-type diffusion layers in the semiconductor region, and forming a suicide film whic... | 02/27/2007 |
| 7169682 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device comprising: a first step of successively forming a silicon oxide film and a silicon nitride film on a silicon substrate, followed by forming a silicon nitride oxide film or a multil... | 01/30/2007 |
| 7109076 | Method of manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device made by its method Mutual diffusion of impurities in a gate electrode is suppressed near a boundary between an n-channel type MISFET and a p-channel type MISFET, which adopt a polycide's dual-gate structure. Since a gate electrode of an n-channel type MISFET and a gate electrode of a ... | 09/19/2006 |
| 6784472 | Semiconductor device and method for fabricating the same A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 | 08/31/2004 |
| 6703269 | Method to form gate conductor structures of dual doped polysilicon A method for manufacturing a semiconductor chip which has transistors is disclosed. The transistors include first type transistors which have a first type of doping and second type transistors which have a second type of doping different than the first ty... | 03/09/2004 |
| 6703670 | Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention ... | 03/09/2004 |
| 6700163 | Selective silicide blocking A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has suicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area a... | 03/02/2004 |
| 6699744 | Method of forming a MOS transistor of a semiconductor device The disclosure relates to a method of forming a MOS transistor of a semiconductor device and, more particularly, to a method of forming a PMOS transistor of a semiconductor device that minimizes temporary reinforcement and diffusion of dopants for control... | 03/02/2004 |
| 6700170 | Insulated gate transistor having a gate insulator containing nitrogen atoms and fluorine atoms An insulated gate transistor in which nitride oxide film having a nitrogen concentration of 1×1020 (/cm3) or more and containing a halogen element is used as a gate insulator. Because the gate insulator has a nitrogen concentration ... | 03/02/2004 |
| 6696328 | CMOS gate electrode using selective growth and a fabrication method thereof A CMOS gate electrode formed using a selective growth method and a fabrication method thereof, wherein, in the CMOS gate electrode, a first gate pattern of polysilicon germanium (poly-SiGe) is formed on a PMOS region of a semiconductor substrate, and a se... | 02/24/2004 |
| 6693313 | Field effect transistors, field effect transistor assemblies, and integrated circuitry The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a... | 02/17/2004 |
| 6690046 | Semiconductor assemblies, methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates The invention encompasses semiconductor assemblies that include a semiconductor substrate having a first region and a second region defined therein. A first oxide region is on the substrate and covers the first region of the substrate. The first oxide reg... | 02/10/2004 |
| 6677652 | Methods to form dual metal gates by incorporating metals and their conductive oxides Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions ar... | 01/13/2004 |
| 6677194 | Method of manufacturing a semiconductor integrated circuit device A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step... | 01/13/2004 |
