Class 257/E21.636 - Silicided or salicided gate conductors (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.635. This subclass
No. of patents: 168
Last issue date: 08/19/2008

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Number	Title	Issue Date
7413968	Method of manufacturing semiconductor device having gate electrodes of polymetal gate and dual-gate structure A silicon film is formed on a first region and a second region, respectively of a semiconductor substrate; P-type impurities are selectively ion-implanted into the silicon film in the first region; a first annealing is carried out, thereby the P-type impurities impl...	08/19/2008
7344984	Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwante...	03/18/2008
7344934	CMOS transistor and method of manufacture thereof A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. An aluminum-based material is used as a gate dielectric material of a PMOS device, and a hafnium-based material is used as a gate dielectric material of an...	03/18/2008
7326610	Process options of forming silicided metal gates for advanced CMOS devices Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielec...	02/05/2008
7314789	Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. ...	01/01/2008
7282402	Method of making a dual strained channel semiconductor device According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. ...	10/16/2007
7271455	Formation of fully silicided metal gate using dual self-aligned silicide process An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of for...	09/18/2007
7226827	Method for fabricating semiconductor devices having silicided electrodes The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a ...	06/05/2007
7217624	Non-volatile memory device with conductive sidewall spacer and method for fabricating the same The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on ...	05/15/2007
7208409	Integrated circuit metal silicide method Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer i...	04/24/2007
7195969	Strained channel CMOS device with fully silicided gate electrode A strained channel NMOS and PMOS device pair including fully silicided gate electrodes and method for forming the same, the method including providing a semiconductor substrate including NMOS and PMOS device regions including respective gate structures including pol...	03/27/2007
7195983	Programming, erasing, and reading structure for an NVM cell A non-volatile memory (NVM) has a silicon germanium (SiGe) drain and a silicon carbon (SiC) source. The source being SiC provides for a stress on the channel that improves N channel mobility. The SiC also has a larger bandgap than the substrate, which is silicon. Th...	03/27/2007
7192823	Manufacturing method for transistor of electrostatic discharge protection device A manufacturing method for a transistor of an ESD protection device. First, the method forms basic elements on a semiconductor base. Next, a patterned resist layer is used as a mask to perform ion implantation in the emerged drain region so that the dopant can be im...	03/20/2007
7179714	Method of fabricating MOS transistor having fully silicided gate There is provided a method of fabricating a MOS transistor having a fully silicided gate, including forming a gate pattern and gate spacers on a semiconductor substrate, the gate pattern including a lower gate pattern, an insulating layer pattern, and an upper gate ...	02/20/2007
7172967	Methods for forming cobalt layers including introducing vaporized cobalt precursors and methods for manufacturing semiconductor devices using the same The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1...	02/06/2007
7118954	High voltage metal-oxide-semiconductor transistor devices and method of making the same A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polys...	10/10/2006
7105429	Method of inhibiting metal silicide encroachment in a transistor A method inhibits metal silicide encroachment in channel regions in a transistor that uses metal silicide as an electrical contact to its terminals. A metal layer is deposited overlying the transistor. A first anneal that is a low temperature anneal forms metal sili...	09/12/2006
6690072	Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where t...	02/10/2004
6673665	Semiconductor device having increased metal silicide portions and method of forming the semiconductor The surface area of silicon lines which receives a silicide portion is increased to decrease the line resistance in narrow polysilicon lines, such as gate electrodes. Sidewall spacers are formed such that an upper portion of the line sidewall is exposed s...	01/06/2004
6670680	Semiconductor device comprising a dual gate CMOS A dual gate type CMOS device according to the present invention includes a silicon substrate having a trench in the main surface and a gate electrode including a polysilicon film and a tungsten silicide film formed above the main surface via a gate insula...	12/30/2003
6657265	Semiconductor device and its manufacturing method A semiconductor device includes metal silicide films formed on the surface of a source-drain region and of a gate electrode. On the metal silicide films, impurity regions are formed of a conductivity type opposite to the conductivity type of the source-dr...	12/02/2003
6642093	Method for manufacturing a semiconductor device According to the present invention, a method for manufacturing a semiconductor device forms a cobalt silicide film 11 on source/drain regions 7a and 7b and a gate electrode 4 of transistors in the logic circuit region, making it possible to form a high-pe...	11/04/2003
6642094	Complementary transistors having respective gates formed from a metal and a corresponding metal-silicide A method of forming a first and second transistor. The method provides a semiconductor surface (20). Th method also forms a gate dielectric (30) adjacent the semiconductor surface. Further, the method forms a first transistor gate electrode (902	11/04/2003
6638803	Semiconductor device and method for manufacturing the same Isolation regions 12 are formed on a silicon substrate 10 to isolate NMOS and PMOS regions in which to form NMOS and PMOS transistors respectively. A silicon oxide film 14 and an amorphous silicon film 16 are formed as a gate insulating film on the silico...	10/28/2003
6617230	Use of selective ozone teos oxide to create variable thickness layers and spacers A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is described. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressu...	09/09/2003
6602807	Use of linear injectors to deposit uniform selective ozone TEOS oxide film by pulsing reactants on and off A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperature...	08/05/2003
6599793	Memory array with salicide isolation The present invention provides a memory array fabricated by complementary metal-oxide-semiconductor salicide process. The memory array comprises a semiconductor substrate. Multitudes of first isolation devices are aligned in the semiconductor substrate an...	07/29/2003
6589836	One step dual salicide formation for ultra shallow junction applications A process for formation of metal silicide on elements of an NMOS device and on elements of a PMOS device, wherein the metal silicide formed on elements of the PMOS device is thinner than the metal silicide simultaneously formed on elements of said NMOS de...	07/08/2003
6570231	Semiconductor device with varying width electrode An n-channel active region, a p-channel active region and an isolation insulating film are formed, and a silicon film is deposited via a gate insulating film. After introducing n-type impurities into the n-channel region and p-type impurities into the p-c...	05/27/2003
6566717	Integrated circuit with silicided ESD protection transistors An electrostatic discharge (ESD) protection circuit for protecting an internal device from an ESD is disclosed. The ESD protection circuit includes an NMOS transistor connected to a ground voltage terminal having silicide layers on a gate electrode and on...	05/20/2003
6555885	Semiconductor device and method of manufacturing the same A semiconductor device having a gate electrode structure including at least a metal film and a polysilicon film is disclosed. The polysilicon film of the semiconductor is doped with impurities several times so that an upper portion of the polysilicon film...	04/29/2003
6552400	Semiconductor device and method of manufacturing the same Disclosed herein is a semiconductor device wherein element active regions for an N channel region and a P channel region are formed so as to adjoin each other, and gate electrode is formed so as to stride over both channel regions and an element isolation...	04/22/2003
6548875	Sub-tenth micron misfet with source and drain layers formed over source and drains, sloping away from the gate A semiconductor device having a low channel resistance without degrading transistor characteristics even for the 0.1 μm generation or later, and also: a manufacturing method of the device. The method includes fabricating source/drain electrodes and a gat...	04/15/2003
6544829	Polysilicon gate salicidation A method of fabricating a substantially completely silicided polysilicon gate electrode in a CMOS process flow. A hard mask material is formed on an integrated circuit substrate, where the integrated circuit substrate includes an unpatterned polysilicon l...	04/08/2003
6541328	Method of fabricating metal oxide semiconductor transistor with lightly doped impurity regions formed after removing spacers used for defining higher density impurity regions In a method of fabricating a metal oxide semiconductor (MOS) transistor with a lightly doped drain (LDD) structure without spacers, gate electrodes and spacers are formed on a semiconductor substrate. A high density source/drain region is formed using the...	04/01/2003
6528401	Method for fabricating polycide dual gate in semiconductor device Method for fabricating a polycide dual gate in a semiconductor device fabricates a dual gate having polycide gate electrodes. The polycide can be a cobalt polycide, for example. The method can include forming polysilicon pattern layers on a first and a se...	03/04/2003
6528381	Method of forming silicide A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which als...	03/04/2003
6518130	Method for forming a semiconductor device having a DRAM region and a logic region on the substrate A semiconductor device comprising a plurality of first transistors formed in a first region of a semiconductor substrate and a plurality of second transistors formed in a second region of the semiconductor substrate, wherein each of the first and second t...	02/11/2003
6518155	Device structure and method for reducing silicide encroachment A semiconductor device having a novel spacer structure and method of fabrication. The present invention describes a semiconductor device which has an electrode with a first thickness. A silicide layer having a second thickness is formed on the electrode. ...	02/11/2003
6506647	Method for fabricating a semiconductor integrated circuit device A method for fabricating a semiconductor integrated circuit device including a memory cell of a MISFET and a capacitor element formed in a memory cell-forming region of a semiconductor substrate, and an n channel-type MISFET and a p channel-type MISFET in...	01/14/2003

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Class 257/E21.636 - Silicided or salicided gate conductors (EPO)