Did You Know...
...that it was melting ice cream that inspired the invention of the outboard motor? It was a lovely August day and Ole Evinrude was rowing his boat to his favorite island picnic spot. As he rowed, he watched his ice cream melt and wished he had a faster way to get to the island. At that moment the idea for the outboard motor was born!
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| Number | Title | Issue Date |
| 6111298 | Etch stop layer formed within a multi-layered gate conductor to provide for reduction of channel length A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of tra... | 08/29/2000 |
| 6110767 | Reversed MOS A new method for fabricating a reversed MOS structure in order to provide latchup immunity in the manufacture of integrated circuits is described. An active area is provided in a semiconductor substrate separated from other active areas by isolation regio... | 08/29/2000 |
| 6103559 | Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication A method is provided for fabricating a semiconductor device, the method including forming a first dielectric layer above a structure and forming an island of a sacrificial layer above the first dielectric layer. The method also includes introducing a firs... | 08/15/2000 |
| 6096641 | Method of manufacturing semiconductor device A tungsten nitride (6b) is provided also on side surface of a tungsten (6c), to increase an area where the tungsten (6c) and the tungsten nitride (6b) are in contact with each other. On a gate insulating film (2), a polysilicon side wall (5) having high a... | 08/01/2000 |
| 6087211 | Method for forming a semiconductor device having non-volatile memory cells, High-voltage transistors, and low-voltage, deep sub-micron transistors A semiconductor device having memory cells, high-voltage CMOS transistors, and low-voltage, deep sub-micron CMOS transistors is formed in a process that allows the same low-voltage device parameters to be used regardless of whether the low-voltage transis... | 07/11/2000 |
| 6017784 | Manufacture method of semiconductor device with suppressed impurity diffusion from gate electrode A method of manufacturing a semiconductor device having fine MOS transistors includes a step of forming a MOS transistor structure on a semiconductor substrate, the MOS transistor structure having an insulated gate electrode, and a step of depositing an i... | 01/25/2000 |
| 5959333 | Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor Diffusion of dopants within the gate of the transistor and/or the source/drain regions can be inhibited by the ion co-implantation of impurities in addition to the ion implantation of the n-type or p-type dopants. Implanting a combination of nitrogen and ... | 09/28/1999 |
| 5933721 | Method for fabricating differential threshold voltage transistor pair A method of establishing a differential threshold voltage during the fabrication of first and second IGFETs having like conductivity type is disclosed. A dopant is introduced into the gate electrode of each transistor of the pair. The dopant is differenti... | 08/03/1999 |
| 5897349 | Method for fabricating a capped gate conductor A gate structure in a CMOS is fabricated wherein the encapsulation material is self-aligned with the gate conductor and the gate channel. The gate conductor is formed subsequent to the device doping and heat cycles for formulation of the source and drain ... | 04/27/1999 |
| 5885861 | Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor Diffusion of dopants within the gate of the transistor and/or the source/drain regions can be inhibited by the ion co-implantation of impurities in addition to the ion implantation of the n-type or p-type dopants. Implanting a combination of nitrogen and ... | 03/23/1999 |
| 5854115 | Formation of an etch stop layer within a transistor gate conductor to provide for reduction of channel length A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of tra... | 12/29/1998 |
| 5843835 | Damage free gate dielectric process during gate electrode plasma etching In a CMOS device uses a thin oxide film as a gate dielectric film, gate electrode plasma etching frequently induces gate dielectric damage. This invention discloses a process which can form a damage free gate dielectric even though there is plasma nonunif... | 12/01/1998 |
| 5783469 | Method for making nitrogenated gate structure for improved transistor performance A method of fabricating an integrated circuit in which nitrogen is incorporated into the gate dielectric and transistor gate. The method comprises the providing of a semiconductor substrate that has a p-well and a laterally displaced n-well, each includin... | 07/21/1998 |
| 5654570 | CMOS gate stack A gate structure in a CMOS is fabricated wherein the encapsulation material is self-aligned with the gate conductor and the gate channel. The gate conductor is formed subsequent to the device doping and heat cycles for formulation of the source and drain ... | 08/05/1997 |
| 5612244 | Insulated gate semiconductor device having a cavity under a portion of a gate structure and method of manufacture An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor substrate (11). A gate oxide layer (26) is formed on... | 03/18/1997 |
| 5563093 | Method of manufacturing fet semiconductor devices with polysilicon gate having large grain sizes The present invention provides the method of manufacturing a dual-gate CMOS device which has high transconductance and improved breakdown voltage, in which depletion in the interface between a gate oxide and a gate electrode is prevented without the incre... | 10/08/1996 |
| 5541132 | Insulated gate semiconductor device and method of manufacture An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor material (11). A gate oxide layer (26) is formed on ... | 07/30/1996 |
| 5273914 | Method of fabricating a CMOS semiconductor devices An ion implantation stopper is formed on a gate electrode extending on a substrate. When ions are implanted into the substrate to form an LDD layer or source and drain regions in the substrate, the stopper functions to prevent the gate electrode from bein... | 12/28/1993 |
| 5036019 | Method of producing a complementary-type semiconductor device A method of producing a MIS transistor such as a MOS transistor has a P type and an N type channel transistors. P type and N type well regions are provided with the N type and the P type channel transistors, respectively. Both the P type and the N type we... | 07/30/1991 |
| 5030582 | Method of fabricating a CMOS semiconductor device An ion implantation stopper is formed on a gate electrode extending on a substrate. When ions are implanted into the substrate to form an LDD layer or source and drain regions in the substrate, the stopper functions to prevent the gate electrode from bein... | 07/09/1991 |
| 4978626 | LDD transistor process having doping sensitive endpoint etching An LDD transistor is formed by using a process which insures that a layer of gate oxide is not inadvertently etched into and is not ruptured by static electrical charges. At least two thicknesses of gate electrode material of varying doping levels are for... | 12/18/1990 |
| 4637836 | Profile control of boron implant The ion implantation of a silicon structure isolated from a semiconductor substrate by a layer of silicon dioxide with boron ions to render it p type conductive is improved by initially doping the silicon with phosphorus ions. The presence of the phosphor... | 01/20/1987 |
| 4462151 | Method of making high density complementary transistors A simple process is provided which forms a bulk CMOS structure by depositing a layer of material which resists oxidation, e.g., a barrier layer of silicon nitride on an N- semiconductor substrate, forming a P well in the substrate through a given segment ... | 07/31/1984 |
| 4420872 | Method of manufacturing a semiconductor device A method of manufacturing an integrated circuit having at least an insulated gate field effect transistor (IGFET). Provided on the silicon surface are successively a gate oxide layer and a doped silicon layer which are patterned by etching by means of a s... | 12/20/1983 |
