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| Number | Title | Issue Date |
| 7432146 | Semiconductor device and manufacturing method thereof To make it possible to obtain a sharp impurity profile without presenting a disadvantage such as an increase in parasitic resistance or the like using a laser annealing method to thereby meet sufficiently the requirements for making a semiconductor element finer and... | 10/07/2008 |
| 7432136 | Transistors with controllable threshold voltages, and various methods of making and operating same In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, the active layer being doped with a first type of dopant material, the bulk substrate having an inner well f... | 10/07/2008 |
| 7432167 | Method of fabricating a strained silicon channel metal oxide semiconductor transistor The present invention provides a method of fabricating strained silicon channel MOS transistor, comprising providing a substrate, forming at least a gate structure on the substrate, forming a mask layer on the gate structure, performing an etching process to form tw... | 10/07/2008 |
| 7416931 | Methods for fabricating a stress enhanced MOS circuit Methods are provided for fabricating a stress enhanced MOS circuit. One method comprises the steps of depositing a stressed material overlying a semiconductor substrate and patterning the stressed material to form a stressed dummy gate electrode overlying a channel ... | 08/26/2008 |
| 7413946 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 08/19/2008 |
| 7414277 | Memory cell having combination raised source and drain and method of fabricating same A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, w... | 08/19/2008 |
| 7410876 | Methodology to reduce SOI floating-body effect A method for making a semiconductor device, comprising (a) providing a structure comprising a gate electrode (207) disposed on a substrate (203); (b) creating first (213) and second (214) pre-amorphization implant regions in the substrate... | 08/12/2008 |
| 7410875 | Semiconductor structure and fabrication thereof A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in... | 08/12/2008 |
| 7402484 | Methods for forming a field effect transistor Methods for forming a field effect transistor are disclosed. An illustrated method comprises: forming a gate electrode on a substrate; and forming a nitride layer on at least a part of the gate electrode and the substrate. ... | 07/22/2008 |
| 7402479 | CMOS image sensor and fabricating method thereof A fabricating method of a CMOS image sensor includes the steps of: forming a transfer gate on a semiconductor substrate where a device isolation layer is formed; forming a first n-type ion implantation region for a photodiode beneath a surface of the semiconductor s... | 07/22/2008 |
| 7390711 | MOS transistor and manufacturing method thereof A MOS transistor including a gate insulation layer and a gate electrode layer on a channel region of a semiconductor substrate. A gate spacer layer is formed on a sidewall of the electrode layer and the insulation layer. The transistor includes a deep extended sourc... | 06/24/2008 |
| 7381623 | Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second ga... | 06/03/2008 |
| 7365010 | Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same Methods of fabricating semiconductor devices having a carbon-containing metal silicide layer and semiconductor devices fabricated by the methods are provided. A representative method includes the steps of preparing a semiconductor substrate and forming a gate electr... | 04/29/2008 |
| 7348248 | CMOS transistor with high drive current and low sheet resistance A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate dielectric over a substrate, a gate electrode over the gate dielectric, a slim gate spacer along a side of the gate electrode, and a source/drain re... | 03/25/2008 |
| 7348233 | Methods for fabricating a CMOS device including silicide contacts Methods are provided for fabricating a CMOS device having a silicon substrate including a first N-type region and a second P-type region. The method includes the steps of forming a first gate electrode overlying the first N-type region and a second gate electrode ov... | 03/25/2008 |
| 7344984 | Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwante... | 03/18/2008 |
| 7329570 | Method for manufacturing a semiconductor device An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first well in a low voltage/medium voltage (LV/MV) region for a logic device, ... | 02/12/2008 |
| 7326622 | Method of manufacturing semiconductor MOS transistor device A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer... | 02/05/2008 |
| 7319061 | Method for fabricating electronic device In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extensi... | 01/15/2008 |
| 7314789 | Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. ... | 01/01/2008 |
| 7300832 | Semiconductor manufacturing method using two-stage annealing A method of semiconductor device manufacture provided includes forming a gate insulating layer upon a single crystal semiconductor substrate, forming a gate electrode made from a polycrystal conductive film upon the gate insulating layer, implanting impurity in the ... | 11/27/2007 |
| 7282416 | Method for fabricating electronic device In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extensi... | 10/16/2007 |
| 7282402 | Method of making a dual strained channel semiconductor device According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. ... | 10/16/2007 |
| 7279406 | Tailoring channel strain profile by recessed material composition control The present invention facilitates semiconductor fabrication by providing methods of fabrication that tailor applied strain profiles to channel regions of transistor devices. A strain profile is selected for the channel regions (104). Recessed regions are form... | 10/09/2007 |
| 7259056 | Method for manufacturing semiconductor device In a method for manufacturing a semiconductor device, gate insulation films and gate electrodes are first formed on a substrate. An impurity is implanted into each gate electrode. Next, a first heat treatment is performed to the substrate for diffusing the impurity ... | 08/21/2007 |
| 7259054 | Method of manufacturing a semiconductor device that includes a process for forming a high breakdown voltage field effect transistor With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type s... | 08/21/2007 |
| 7253060 | Gate-all-around type of semiconductor device and method of fabricating the same A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mo... | 08/07/2007 |
| 7253039 | Method of manufacturing CMOS transistor by using SOI substrate In a method of manufacturing a CMOS transistor, an n-channel MOS transistor is formed on an upper MOS transistor in a first region of an SOI substrate having first and second regions. Next, an insulating layer of the SOI substrate is exposed by removing an upper sil... | 08/07/2007 |
| 7247535 | Source/drain extensions having highly activated and extremely abrupt junctions A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the ... | 07/24/2007 |
| 7226833 | Semiconductor device structure and method therefor Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying l... | 06/05/2007 |
| 7195983 | Programming, erasing, and reading structure for an NVM cell A non-volatile memory (NVM) has a silicon germanium (SiGe) drain and a silicon carbon (SiC) source. The source being SiC provides for a stress on the channel that improves N channel mobility. The SiC also has a larger bandgap than the substrate, which is silicon. Th... | 03/27/2007 |
| 7189624 | Fabrication method for a semiconductor device including a semiconductor substrate formed with a shallow impurity region A method of manufacturing a semiconductor device includes forming isolation regions, a gate insulator film and gate electrodes, implanting in the silicon substrate with impurity ions, annealing to recover crystallinity of the implanted silicon substrate without diff... | 03/13/2007 |
| 7118977 | System and method for improved dopant profiles in CMOS transistors According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a gate stack on an outer surface of a semiconductor body. First and second sidewall bodies are formed on opposing sides of the gate stack. A first reces... | 10/10/2006 |
| 7119369 | FET having epitaxial silicon growth A field-effect transistor has a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, and an extension of epitaxial monocrystalline ma... | 10/10/2006 |
| 7052965 | Methods of fabricating MOS field effect transistors with pocket regions using implant blocking patterns MOSFETs with pocket regions are fabricated. A gate electrode layer is formed on a semiconductor substrate; and lightly doped drain regions are formed in the semiconductor substrate adjacent the gate electrode layer. A blocking pattern is formed on the semiconductor ... | 05/30/2006 |
| 7050345 | Memory device and method with improved power and noise characteristics A memory device and method with reduced power consumption and improved noise performance. An illustrative embodiment provides a random access memory with an array of plural memory bit cells, having bit-latches coupled between bit-true pass-gates and bit-compliment p... | 05/23/2006 |
| 6703663 | CMOS device using additional implant regions to enhance ESD performance and device manufactured thereby A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with s... | 03/09/2004 |
| 6696327 | Method for making a semiconductor device having a high-k gate dielectric A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, then forming a capping layer on the high-k gate dielectric layer. After oxidizing the capping layer to form a capping die... | 02/24/2004 |
| 6690060 | Field effect transistor and method of fabricating the same by controlling distribution condition of impurity region with implantation of additional ion A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide ... | 02/10/2004 |
| 6690050 | Semiconductor device and its manufacture In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain regions are formed, and contact holes are formed. Side wall ... | 02/10/2004 |
