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| Number | Title | Issue Date |
| 7439140 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 10/21/2008 |
| 7432160 | Semiconductor devices including transistors having three dimensional channels and methods of fabricating the same Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional struct... | 10/07/2008 |
| 7432167 | Method of fabricating a strained silicon channel metal oxide semiconductor transistor The present invention provides a method of fabricating strained silicon channel MOS transistor, comprising providing a substrate, forming at least a gate structure on the substrate, forming a mask layer on the gate structure, performing an etching process to form tw... | 10/07/2008 |
| 7416931 | Methods for fabricating a stress enhanced MOS circuit Methods are provided for fabricating a stress enhanced MOS circuit. One method comprises the steps of depositing a stressed material overlying a semiconductor substrate and patterning the stressed material to form a stressed dummy gate electrode overlying a channel ... | 08/26/2008 |
| 7413946 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 08/19/2008 |
| 7411245 | Spacer barrier structure to prevent spacer voids and method for forming the same A semiconductor device includes a spacer adjacent a gate structure. A protection layer covers oxide portions of the spacer surface such that subsequent manufacturing operations such as wet oxide etches and strips, do not produce voids in the spacers. A method for fo... | 08/12/2008 |
| 7410876 | Methodology to reduce SOI floating-body effect A method for making a semiconductor device, comprising (a) providing a structure comprising a gate electrode (207) disposed on a substrate (203); (b) creating first (213) and second (214) pre-amorphization implant regions in the substrate... | 08/12/2008 |
| 7402496 | Complementary metal-oxide-semiconductor device and fabricating method thereof A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a f... | 07/22/2008 |
| 7402497 | Transistor device having an increased threshold stability without drive current degradation By removing a portion of a halo region or by avoiding the formation of the halo region within the extension region, which may be subsequently formed on the basis of a re-grown semiconductor material, the threshold roll off behavior may be significantly improved, whe... | 07/22/2008 |
| 7371630 | Patterned backside stress engineering for transistor performance optimization Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance. ... | 05/13/2008 |
| 7371648 | Method for manufacturing a transistor device having an improved breakdown voltage and a method for manufacturing an integrated circuit using the same The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a... | 05/13/2008 |
| 7335948 | Integrated circuit incorporating higher voltage devices and low voltage devices therein An integrated circuit formed on a semiconductor substrate and configured to accommodate higher voltage devices and low voltage devices therein. In one embodiment, the integrated circuit includes a switch formed on the semiconductor substrate and a driver switch of a... | 02/26/2008 |
| 7314789 | Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. ... | 01/01/2008 |
| 7288451 | Method and structure for forming self-aligned, dual stress liner for CMOS devices A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of th... | 10/30/2007 |
| 7282402 | Method of making a dual strained channel semiconductor device According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. ... | 10/16/2007 |
| 7279406 | Tailoring channel strain profile by recessed material composition control The present invention facilitates semiconductor fabrication by providing methods of fabrication that tailor applied strain profiles to channel regions of transistor devices. A strain profile is selected for the channel regions (104). Recessed regions are form... | 10/09/2007 |
| 7265002 | Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel A method for making a semiconductor device may include providing a substrate, and forming at least one MOSFET adjacent the substrate by forming a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of la... | 09/04/2007 |
| 7265012 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 09/04/2007 |
| 7250332 | Method for fabricating a semiconductor device having improved hot carrier immunity ability The present invention discloses a method for fabricating a semiconductor device. A substrate is provided. At least one first and second gate structure, having sidewalls, are included on a surface of the substrate. A first ion implantation process is performed to for... | 07/31/2007 |
| 7247532 | High voltage transistor and method for fabricating the same A high voltage transistor operating through a high voltage and a method for fabricating the same are provided. The high voltage transistor includes: an insulation layer on a substrate; an N+-type drain junction region on the insulation layer; an N−... | 07/24/2007 |
| 7232744 | Method for implanting dopants within a substrate by tilting the substrate relative to the implant source The present invention provides a method for implanting a dopant in a substrate and a method for manufacturing a semiconductor device. The method for implanting a dopant, among other steps, including tilting a substrate (310) located on or over an implant plat... | 06/19/2007 |
| 7220626 | Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; fo... | 05/22/2007 |
| 7211869 | Increasing carrier mobility in NFET and PFET transistors on a common wafer Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop layers, overlying the transistors with stress being wholly or partial... | 05/01/2007 |
| 7202131 | Method of fabricating semiconductor device A method of fabricating a semiconductor device is provided, by which leakage current is reduced by minimizing electron or hole density in a source/drain forming a P/N junction with a transistor channel area. The method includes forming a gate insulating layer on a s... | 04/10/2007 |
| 7183158 | Method of fabricating a non-volatile memory A method of fabricating a nonvolatile memory is provided. The method includes forming a bottom dielectric layer, a charge trapping layer, a top dielectric layer and a conductive layer on the substrate sequentially. Portions of conductive layer, top dielectric layer,... | 02/27/2007 |
| 7176095 | Bi-modal halo implantation Methods of fabricating halo regions are provided. In one aspect, a method is provided of fabricating a first halo region and a second halo region for a circuit device of a first conductivity type and having a gate structure with first and second sidewalls. The first... | 02/13/2007 |
| 7163856 | Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into t... | 01/16/2007 |
| 7115462 | Processes providing high and low threshold p-type and n-type transistors Methods of fabricating negative-channel metal-oxide semiconductor (NMOS) devices and positive-channel metal-oxide semiconductor (PMOS) devices having complementary threshold voltages are described. Elements of lower-threshold voltage NMOS devices are formed at first... | 10/03/2006 |
| 7045410 | Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI) A method (200) of forming an isolation structure is disclosed, and includes forming a patterned isolation hard mask layer (206, 212) having an isolation opening associated therewith over a semiconductor body. An implant into the isolation opening is th... | 05/16/2006 |
| 6703271 | Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The compos... | 03/09/2004 |
| 6703688 | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p... | 03/09/2004 |
| 6693331 | Method of fabricating dual threshold voltage n-channel and p-channel MOSFETS with a single extra masked implant operation A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions ... | 02/17/2004 |
| 6690060 | Field effect transistor and method of fabricating the same by controlling distribution condition of impurity region with implantation of additional ion A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide ... | 02/10/2004 |
| 6686233 | Integration of high voltage self-aligned MOS components The invention relates to a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, in an n-well CMOS process by adding solely two additional process steps to a conventi... | 02/03/2004 |
| 6682965 | Method of forming n-and p- channel field effect transistors on the same silicon layer having a strain effect A method for forming a Field Effect Transistor (FET) within a strain effect semiconductor layer is disclosed, whereby the source and drain of the FET are formed only in the strain effect silicon layer. The FET may be formed as a gate electrode of a p-chan... | 01/27/2004 |
| 6677192 | Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p... | 01/13/2004 |
| 6677194 | Method of manufacturing a semiconductor integrated circuit device A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step... | 01/13/2004 |
| 6674100 | SiGeC-based CMOSFET with separate heterojunctions Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in... | 01/06/2004 |
| 6667200 | Method for forming transistor of semiconductor device A method for forming a transistor of a semiconductor device, including the step of forming channel layers of a first and a second conductive types, performing high temperature thermal process to form stabilized channel layers and forming an epitaxial chan... | 12/23/2003 |
| 6667524 | Semiconductor device with a plurality of semiconductor elements A first semiconductor element is a transistor for use in a memory cell region, and a second semiconductor element is a transistor for use in a peripheral circuit region. A first total impurity concentration of a first impurity diffusion region and a secon... | 12/23/2003 |
