Did You Know...
...that the Eveready Battery began as an invention called the "electric flowerpot," which was a tube with a battery and light bulb inside? The idea was to fasten this gizmo to the side of a flowerpot so it would illuminate the flowers from the bottom. The idea died on the vine and the businessman who licensed the flower pot, Conrad Huber, was left with a pile of useless tubes -- until he found a way to market them as batteries to light the world!
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| Number | Title | Issue Date |
| 7442601 | Stress enhanced CMOS circuits and methods for their fabrication A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS tr... | 10/28/2008 |
| 7439124 | Method of manufacturing a semiconductor device and semiconductor device Method of manufacturing a semiconductor device includes: forming a substrate protection film to cover an n-type FET forming region having a first gate electrode and a p-type FET forming region having a second gate electrode; opening the p-type FET forming region by ... | 10/21/2008 |
| 7439105 | Metal gate with zirconium A gate electrode (202) for a transistor including a metal gate structure (207) containing zirconium and a polycrystalline silicon cap (209) located there over. The metal gate structure (207) is located over a gate dielectric (205).... | 10/21/2008 |
| 7435639 | Dual surface SOI by lateral epitaxial overgrowth A semiconductor process and apparatus provide a planarized hybrid substrate (18) by exposing a buried oxide layer (80) in a first area (99), selectively etching the buried oxide layer (80) to expose a first semiconductor layer (70)... | 10/14/2008 |
| 7427542 | Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device including a complementary metal oxide semiconductor (CMOS) and a bipolar junction transistor (BJT), the method comprising the steps of: forming a gate oxide layer on a substrate having a p-type and an n-type well; rem... | 09/23/2008 |
| 7419864 | Semiconductor device and method of manufacturing the same A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a... | 09/02/2008 |
| 7413946 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 08/19/2008 |
| 7413939 | Method of growing a germanium epitaxial film on insulator for use in fabrication of CMOS integrated circuit A method of fabricating a silicon-germanium CMOS includes preparing a silicon substrate wafer; depositing an insulating layer on the silicon substrate wafer; patterning and etching the insulating layer; depositing a layer of polycrystalline germanium on the insulati... | 08/19/2008 |
| 7413944 | CMOS image sensor and method of manufacturing the same In a CMOS image sensor manufacturing process, heavily doped p type impurity ions (for example, B) are implanted in a dummy moat region when the heavily doped p type impurity ions is implanted in a PMOS transistor region, so that metal ion contamination is removed. A... | 08/19/2008 |
| 7405436 | Stressed field effect transistors on hybrid orientation substrate A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device locate... | 07/29/2008 |
| 7402477 | Method of making a multiple crystal orientation semiconductor device A method of having transistors formed in enhanced performance crystal orientations begins with a wafer having a semiconductor substrate (12,52) of a first surface orientation, a thin etch stop layer (14,54) on the semiconductor substrate, a buried oxid... | 07/22/2008 |
| 7402476 | Method for forming an electronic device An electronic device is formed by forming a first and second layer overlying a plurality of transistor locations. An etch is performed to remove portions of the first and second layers to expose a portion of the plurality of transistor locations, while other portion... | 07/22/2008 |
| 7396755 | Process and integration scheme for a high sidewall coverage ultra-thin metal seed layer The present invention provides a method of forming a metal seed layer 100. The method includes physical vapor deposition of seed metal 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also ... | 07/08/2008 |
| 7393736 | Atomic layer deposition of ZrHfSnOfilms as high k gate dielectrics The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO2), hafnium oxide (HfO2) and tin oxide (SnO2) acting as a single dielectric layer with a formula of ZrXHfYSn... | 07/01/2008 |
| 7384833 | Stress liner for integrated circuits In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a... | 06/10/2008 |
| 7378306 | Selective silicon deposition for planarized dual surface orientation integration A semiconductor process and apparatus provide a planarized hybrid substrate (225) having a more uniform polish surface (300) by thickening an SOI semiconductor layer (210) in relation to a previously or subsequently formed epitaxial silicon laye... | 05/27/2008 |
| 7368339 | Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted region... | 05/06/2008 |
| 7368796 | Metal gate engineering for surface P-channel devices A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix | 05/06/2008 |
| 7364959 | Method for manufacturing a MOS transistor A method for manufacturing a MOS transistor integrated into a chip of semi-conductive material comprising a first and a second active region which extend from the inside of the chip to a surface of the chip. The method comprises the steps of: a) forming a layer of i... | 04/29/2008 |
| 7364972 | Semiconductor device A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first cir... | 04/29/2008 |
| 7361932 | Semiconductor device and method for fabricating the same A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a... | 04/22/2008 |
| 7361538 | Transistors and methods of manufacture thereof Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over the gate dielectric by exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (... | 04/22/2008 |
| 7354836 | Technique for forming a strained transistor by a late amorphization and disposable spacers By using a disposable spacer approach for forming drain and source regions prior to an amorphization process for re-crystallizing a semiconductor region in the presence of a stressed spacer layer, possibly in combination with enhanced anneal techniques, such as lase... | 04/08/2008 |
| 7348202 | CMOS image sensor and method for fabricating the same An image sensor includes a semiconductor substrate; a pixel array disposed on the semiconductor substrate; and an insulating interlayer, formed on the semiconductor substrate, having a trench coinciding with the disposition of the pixel array, the trench having unif... | 03/25/2008 |
| 7348231 | Methods of fabricating semiconductor devices having insulating layers with differing compressive stresses Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substr... | 03/25/2008 |
| 7344933 | Method of forming device having a raised extension region A method is disclosed of forming an extension region for a transistor having a gate structure overlying a compound semiconductor layer. An anneal is used either before or after deep source/drain implantation to diffuse a dopant from a raised region adjacent the gate... | 03/18/2008 |
| 7344929 | Method for manufacturing an integrated circuit using a capping layer having a degree of reflectivity The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a capping layer (210) over a tran... | 03/18/2008 |
| 7344934 | CMOS transistor and method of manufacture thereof A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. An aluminum-based material is used as a gate dielectric material of a PMOS device, and a hafnium-based material is used as a gate dielectric material of an... | 03/18/2008 |
| 7341904 | Capacitorless 1-transistor DRAM cell and fabrication method A semiconductor device is fabricated by forming a trench in a semiconductor body. A region of dielectric material is formed within at least a lower portion of the trench. An upper portion of the semiconductor body is doped. A cutout is formed in the semiconductor ma... | 03/11/2008 |
| 7332433 | Methods of modulating the work functions of film layers Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where t... | 02/19/2008 |
| 7323377 | Increasing self-aligned contact areas in integrated circuits using a disposable spacer In one embodiment, a method of fabricating an integrated circuit includes the steps of: (i) forming composite spacers on sidewalls of a transistor gate, each of the composite spacers comprising a first liner having a stepped portion and a disposable spacer material ... | 01/29/2008 |
| 7314788 | Standard cell back bias architecture An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transist... | 01/01/2008 |
| 7309628 | Method of forming a semiconductor device A semiconductor device is formed as part of an integrated circuit. The semiconductor device, which is formed in an active semiconductor layer, is surrounded by a guardian that provides a diffusion barrier against contaminants and also provides assistance in avoiding... | 12/18/2007 |
| 7297585 | Method of manufacturing semiconductor device having impurity region under isolation region In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film prevents a well region located under the g... | 11/20/2007 |
| 7297584 | Methods of fabricating semiconductor devices having a dual stress liner In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, an... | 11/20/2007 |
| 7288804 | Electrically programmable π-shaped fuse structures and methods of fabrication thereof Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first te... | 10/30/2007 |
| 7282402 | Method of making a dual strained channel semiconductor device According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. ... | 10/16/2007 |
| 7274055 | Method for improving transistor performance through reducing the salicide interface resistance An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the sour... | 09/25/2007 |
| 7271045 | Etch stop and hard mask film property matching to enable improved replacement metal gate process A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material... | 09/18/2007 |
| 7268029 | Method of fabricating CMOS transistor that prevents gate thinning Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implante... | 09/11/2007 |
