Class 257/E21.631 - Combination of enhancement and depletion transistors (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.616. This subclass
No. of patents: 40
Last issue date: 10/30/2007

Number	Title	Issue Date
7288463	Pulsed deposition layer gap fill with expansion material Conformal dielectric deposition processes supplemented with a deposited expansion material can fill high aspect ratio narrow width gaps with significantly reduced incidence of voids or weak spots. The technique can also be used generally to form composites, such as ...	10/30/2007
7282402	Method of making a dual strained channel semiconductor device According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. ...	10/16/2007
7265421	Insulated-gate field-effect thin film transistors A new Insulated-Gate Field-Effect Thin Film Transistor (Gated-FET) is disclosed. A semiconductor thin film Gated-FET device, comprising: a lightly doped resistive channel region formed on a semiconductor thin film layer, the thickness of the channel comprising the e...	09/04/2007
7087967	LSI device having core and interface regions with SOI layers of different thickness An LSI device includes a core region to which a first driving voltage is applied and an interface region to which a second driving voltage higher than the above first driving voltage is applied. The LSI device includes an SOI substrate and a device separation region...	08/08/2006
6448121	High threshold PMOS transistor in a surface-channel process A buried-channel PMOS device is fabricated simultaneously with a surface-channel device if the gate is doped N-type while the NMOS gates are doped and the P+ source/drain doping is blocked from the "high" P-channel device. In the normal process the "high"...	09/10/2002
6054354	High voltage field effect transistors with selective gate depletion A method of forming field effect transistors (FETS) on a silicon wafer. A gate layer, polysilicon, is formed on a gate dielectric layer (oxide) on the silicon wafer. High voltage device locations are defined and blocked while normal NFETs and PFETs are fo...	04/25/2000
5976938	Method of making enhancement-mode and depletion-mode IGFETs with different gate thicknesses A method of making enhancement-mode and depletion-mode IGFETs with different gate thicknesses is disclosed. The method includes providing a semiconductor substrate with first and second device regions, forming a first gate with a first thickness over the ...	11/02/1999
5969392	Thermal ink jet printheads with power MOS driver devices having enhanced transconductance A high voltage MOS transistor, for use in a thermal ink jet printhead, is fabricated with a single, uniformly thick layer of polysilicon that serves as a field plate over the drift region and a gate over the channel region. The fabrication of the drift re...	10/19/1999
5885874	Method of making enhancement-mode and depletion-mode IGFETS using selective doping of a gate material A method of making enhancement-mode and depletion-mode IGFETs is disclosed. The method includes providing a semiconductor substrate with first and second device regions, forming a gate material over the first and second device regions, implanting a dopant...	03/23/1999
5514610	Method of making an optimized code ion implantation procedure for read only memory devices A process designed to fabricate depletion mode MOSFET devices, for ROM applications, has been developed. A key feature of this fabrication sequence is the ion implantation step used to create the programmable cell. The code implant step is performed throu...	05/07/1996
5266515	Fabricating dual gate thin film transistors A method for fabricating a dual gate thin film transistor using a power MOSFET process having a first gate area (22) made from a monocrystalline silicon. A dielectric layer (25) is formed over the monocrystalline silicon. A first gate electrode (58) conta...	11/30/1993
5257095	Common geometry high voltage tolerant long channel and high speed short channel field effect transistors A field effect device transistor geometry and method of fabrication are described. The FET may be operated from a bias potential that forms an electrical field within the device exceeding a predetermined field strength. The device comprises a semiconducto...	10/26/1993
5229633	High voltage lateral enhancement IGFET A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one cond...	07/20/1993
5139962	MOS fabrication method with self-aligned gate MOS field-effect transistors connected in series on a semiconductor substrate are created by forming at least two first gate electrodes on the substrate, mutually separated by a certain distance, then depositing a polycrystalline conducting layer. The pol...	08/18/1992
5135880	Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one cond...	08/04/1992
5075250	Method of fabricating a monolithic integrated circuit chip for a thermal ink jet printhead A thermal jet ink printing is provided with an improved printhead. The printhead is formed by monolithic integration of MOS logic elements and drivers onto the same silicon substrate containing the resistive elements using a more efficient manufacturing p...	12/24/1991
4892836	Method for manufacturing semiconductor integrated circuits including CMOS and high-voltage electronic devices This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming...	01/09/1990
4849368	Method of producing a two-dimensional electron gas semiconductor device Disclosed is a method of producing a compound semiconductor device comprising an enhancement-mode transistor and a depletion-mode transistor, each of which has a heterojunction and utilizes a two-dimensional electron gas. The method of producing the devic...	07/18/1989
4742379	HEMT with etch-stop A compound semiconductor device comprises an enhancement-mode transistor and a depletion-mode transistor, each of which has a heterojunction and utilizes a two-dimensional electron gas. The method of producing the device comprises the steps of: forming an...	05/03/1988
4721686	Manufacturing integrated circuits containing P-channel MOS transistors and bipolar transistors utilizing boron and arsenic as dopants This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant on the surface of an epitaxial layer, without masking, and arsenic implant in predetermined locations of the epitaxial layer surface by mea...	01/26/1988
4679303	Method of fabricating high density MOSFETs with field aligned channel stops A high-density MOSFET having field oxide self-aligned channel stops for device isolation and an optimal method of fabricating such a device is described. The process provides channel stops underlying and aligned with the edges of a field oxide layer and a...	07/14/1987
4649638	Construction of short-length electrode in semiconductor device A construction process employs an insulating abutment which serves as a guide in the formation of a shortlength electrode in the fabrication of a semiconductor device. The process is particularly useful in construction of extremely short channel asymmetri...	03/17/1987
4600933	Semiconductor integrated circuit structure with selectively modified insulation layer An integrated circuit structure includes a substrate, diffused regions formed in the upper surface of the substrate, and thin and thick insulative regions, polycrystalline regions, and metallic interconnections selectively formed overlying selected areas ...	07/15/1986
4503601	Oxide trench structure for polysilicon gates and interconnects Disclosed is a manufacturing method of forming silicon gate, self-aligned MOS-type devices having submicron dimensions. After forming the gate from a highly doped polysilicon layer using a mask, the structure is subjected to a low temperature (700-750 deg...	03/12/1985
4481704	Method of making an improved MESFET semiconductor device An improved MESFET integrated circuit device with a metal-semiconductor diode as the control element and a source and drain as other device elements is fabricated using a self-aligned gate process which consists of an implanted channel stopper underneath ...	11/13/1984
4315781	Method of controlling MOSFET threshold voltage with self-aligned channel stop A process is provided for fabricating MOSFET devices having field source, gate and drain regions. The threshold voltage of both the channel and field regions of such devices is controlled by forming a comparatively thick oxide film on a semiconductor surf...	02/16/1982
4246044	Method for fabricating semi-conductor devices A process for fabricating semi-conductor devices, such as depletion mode MOS transistors, including the process of doping impurities in to the semi-conductor substrate by using a newly provided oxide layer as a doping mask, and thereafter providing a gate...	01/20/1981
4229755	Fabrication of very large scale integrated circuits containing N-channel silicon gate nonvolatile memory elements A method of fabricating very large scale integrated circuits including N-channel silicon gate nonvolatile memory elements and additional peripheral transistor elements. The nonvolatile memory elements are fabricated as PDS protected drain-source devices c...	10/21/1980
4228447	Submicron channel length MOS inverter with depletion-mode load transistor An improved, high speed n-channel MOS inverter structure including a self-aligned silicon gate depletion-mode load device integrated in series with a nonplanar, submicron channel enhancement-mode switching transistor. The enhancement-mode switching device...	10/14/1980
4206005	Method of making split gate LSI VMOSFET A split gate VMOSFET having an enhancement transistor and a depletion load transistor on opposing sidewalls of a V-groove region. In the process, a differential oxidation rate due to the different crystal orientations of the substrate is used to complete ...	06/03/1980
4205330	Method of manufacturing a low voltage n-channel MOSFET device A novel MOSFET circuit and method of manufacture utilizing a double ion implant process for manufacturing a low voltage high performance n-channel device that includes an enhancement transistor inverter combined with a depletion transistor load. The proce...	05/27/1980
4201997	MESFET semiconductor device and method of making An improved MESFET integrated circuit device with a metal-semiconductor diode as the control element and a source and drain as other device elements is fabricated using a self-aligned gate process which consists of an implanted channel stopper underneath ...	05/06/1980
4138782	Inverter with improved load line characteristic An insulated gate field effect transistor (IGFET) static inverter having an improved load line characteristic is disclosed. The inverter comprises an enhancement mode IGFET active device in a first portion of a semiconductor substrate, having its drain co...	02/13/1979
4104784	Manufacturing a low voltage n-channel MOSFET device A novel MOSFET circuit and method of manufacture utilizing a double ion implant process for manufacturing a low voltage high performance n-channel device that includes an enhancement transistor inverter combined with a depletion transistor load. The proce...	08/08/1978
4080718	Method of modifying electrical characteristics of MOS devices using ion implantation A method is disclosed for selectively modifying the electrical characteristics of MOS devices at a late stage in the fabrication process to form, for example, the "1" and "0" data locations of a ROM, or to form enhancement-and depletion-mode devices. In o...	03/28/1978
4078947	Method for forming a narrow channel length MOS field effect transistor A method for fabricating an N-channel silicon MOS field effect transistor on a P-type substrate. The structure retains the natural isolation between devices and the consequent higher device density in an integrated circuit structure than conventional doub...	03/14/1978
4041518	MIS semiconductor device and method of manufacturing the same A metal-insulator semiconductor (MIS) device is manufactured by initially forming, on a semiconductor substrate, an insulating film having a hole therethrough and depositing silicon on the substrate to form a first monocrystalline silicon film in the hole...	08/09/1977
4003071	Method of manufacturing an insulated gate field effect transistor A method of manufacturing an insulated gate field effect transistor (hereinafter referred to as IGFET) of metal-insulating film-semiconductor construction in which a predetermined amount of impurity is introduced into the insulating film to produce immobi...	01/11/1977
3983572	Semiconductor devices The invention is concerned with methods for producing improved semiconductor devices. The invention is advantageously employable in the fabrication of insulated-gate field-effect transistor devices. The problem of accurately aligning the gate electrode ov...	09/28/1976
3967981	Method for manufacturing a semiconductor field effort transistor A method of manufacturing a metal, insulator, semiconductor type field effect transistor (MISFET) is disclosed by which a device is obtained having greatly improved reliability and containing multi-layered wiring. Only three photo-mask processes are used ...	07/06/1976

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Class 257/E21.631 - Combination of enhancement and depletion transistors (EPO)