Class 257/E21.63 - With particular manufacturing method of wells or tubs, e.g., twin tubs, high energy well implants, buried implanted layers for lateral isolation (BILLI) (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.616. This subclass
No. of patents: 59
Last issue date: 10/21/2008

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Number	Title	Issue Date
7439123	Low resistance contact semiconductor device structure A method for making a semiconductor device structure includes producing a substrate having formed thereon a gate with spacers, respective source and drain regions adjacent to the gate and an; disposing a first metallic layer on the gate with spacers, and the source ...	10/21/2008
7419893	Method of manufacturing semiconductor device having triple-well structure and semiconductor device fabricated This patent specification describes methods for fabricating semiconductor device having a plurality of well structures including a triple-well structure. One example of a method for fabricating semiconductor device includes forming a thermally stable film on a first...	09/02/2008
7351628	Atomic layer deposition of CMOS gates with variable work functions Structures, systems and methods for transistors having gates with variable work functions formed by atomic layer deposition are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween....	04/01/2008
7335549	Semiconductor device and method for fabricating the same An N-channel transistor includes: an N-type source region, a gate electrode, a P-type body region, an N-type drain offset region, and a drain contact region, which is an N-type drain region. The transistor further includes a gate insulating film that has a thin oxid...	02/26/2008
7309661	Method for forming gate of semiconductor device Disclosed is a method for forming a gate of a semiconductor device capable of preventing a bridge from being created between adjacent gates due to a nitride polymer. The method includes the steps of forming a gate oxide film, a gate poly-Si film, and a gate W film s...	12/18/2007
7285453	Triple well structure and method for manufacturing the same The present invention discloses a triple well structure, which includes a substrate of a first conductive type, a deep buried well of a second conductive type, a well of a first conductive type, a well ring of a second conductive type, and a well ring of a first con...	10/23/2007
7282402	Method of making a dual strained channel semiconductor device According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. ...	10/16/2007
7273776	Methods of forming a P-well in an integrated circuit device The present invention is generally directed to a method of forming a p-well in an integrated circuit device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial material above an active layer of a substrate, forming a first doped ...	09/25/2007
7211481	Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in ...	05/01/2007
7202120	Semiconductor integrated circuit device and fabrication process thereof A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation f...	04/10/2007
7122867	Triple well structure and method for manufacturing the same The present invention discloses a triple well structure, which includes a substrate of a first conductive type, a deep buried well of a second conductive type, a well of a first conductive type, a well ring of a second conductive type, and a well ring of a first con...	10/17/2006
7071527	Semiconductor element and manufacturing method thereof A p-channel MOSFET (1) includes a semiconductor substrate (2), an epitaxial region (3), a second diffusion region (6), and a drain region. The epitaxial region (3) is formed on the upper surface of the semiconductor substrate (2...	07/04/2006
6680231	High-voltage device process compatible with low-voltage device process A high-voltage device process compatible with a low-voltage device process. A high-voltage device area and a low-voltage device area are defined on an epitaxial layer of a semiconductor substrate. After forming a plurality of first gate structures on the ...	01/20/2004
6656816	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device enables the formation of a well optimized for a fine MOS transistor and a well formed deep with a relatively low concentration for a high voltage MOS transistor without increasing the number of manufacturi...	12/02/2003
6613659	Manufacturing method of gate insulating film of multiple thickness A semiconductor device having a P type well region formed inside a P type semiconductor substrate, on which at least three gate insulating films each having a different thickness are formed. Also, the device has the gate electrode formed extending over th...	09/02/2003
6610585	Method for forming a retrograde implant A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant...	08/26/2003
6600205	Method for making low voltage transistors with increased breakdown voltage to substrate having three different MOS transistors A high-breakdown voltage transistor (30; 30') is disclosed. The transistor (30; 30') is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed i...	07/29/2003
6537893	Substrate isolated transistor A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposit...	03/25/2003
6514824	Semiconductor device with a pair of transistors having dual work function gate electrodes Techniques are described for fabricating a pair of ଲ-identical transistors, in other words, a pair of transistors whose dimensions and electrical characteristics, other than their respective gate electrode work functions, are substantially similar. ...	02/04/2003
6509220	Method of fabricating a high-voltage transistor A method for making a high voltage insulated gate field-effect transistor with one or more JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first epitaxial layer of a second conductivity type so as to f...	01/21/2003
6492710	Substrate isolated transistor A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposit...	12/10/2002
6489190	Method of fabricating a high-voltage transistor A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a fir...	12/03/2002
6482717	Method of manufacturing a semiconductor device including forming well comprising EPI in trench A method for fabricating a semiconductor device by one masking process using selective epitaxial growth, comprising the steps of providing a first conductive silicon substrate having an active region and field regions thereon and having a formed pad oxide...	11/19/2002
6468847	Method of fabricating a high-voltage transistor A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a fir...	10/22/2002
6441440	Semiconductor device and circuit having low tolerance to ionizing radiation Semiconductor devices and integrated circuits that benefit from the advantages of contemporary processing technologies yet are irreparably damaged by ionizing radiation, and methods for making the same. Transistors that are particularly intolerant to ioni...	08/27/2002
6399465	Method for forming a triple well structure A method of forming a triple well structure. A first photoresist layer is formed on a substrate having a first conductive type. A first ion implantation process is performed to form a first well, which has the first conductive type but a dopant concentrat...	06/04/2002
6388295	Semiconductor device and method of manufacturing the same The semiconductor device has a triple well structure. The triple well and other wells have impurity concentration distributions in the depth direction, which are determined in accordance with required function. Thereby, the required performances such as s...	05/14/2002
6376870	Low voltage transistors with increased breakdown voltage to substrate A high-breakdown voltage transistor (30; 30') is disclosed. The transistor (30; 30') is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed i...	04/23/2002
6346463	Method for forming a semiconductor device with a tailored well profile A method for forming a semiconductor device is provided. A base layer is provided. A first epitaxial layer having a first dopant at a first concentration is formed above the base layer. A second epitaxial layer having a second dopant at a second concentra...	02/12/2002
6300661	Mutual implant region used for applying power/ground to a source of a transistor and a well of a substrate An integrated circuit fabrication process is provided for forming, a mutual implant region within a well which is shared by a source region of a transistor residing within the well and a well-tie region coupled to the well, thereby providing a single elec...	10/09/2001
6297133	Method of fabricating well A method of manufacturing wells comprises the step of providing a p-type substrate and then sequentially forming a p-well and n-well with low dosage in the p-type substrate. Thereafter, energy is used to dope n-type ions into the p-well. The triple well f...	10/02/2001
6274444	Method for forming mosfet A method for forming a MOSFET is described. The feature of this invention is that an epitaxial silicon layer with device isolation structures is formed over a substrate, wherein each device isolation structure is made of oxide. The invention need not etch...	08/14/2001
6262457	Method of producing a transistor structure Additional degrees of freedom are provided for optimizing the component properties by combining two doping profiles. The threshold voltage of NMOS or DMOS transistors can be set through the process parameters involved in the introduction and outward diffu...	07/17/2001
6222252	Semiconductor substrate and method for producing the same A semiconductor substrate is provided which can efficiently exhibit intrinsic gettering (IG) effect, is less likely to cause slipping or dislocation, and causes no significant lowering in mechanical strength. The semiconductor substrate has bulk micro def...	04/24/2001
6214674	Method of fabricating high voltage device suitable for low voltage device A method of fabricating a high-voltage device suitable for a low-voltage device. A well formed by ion implantation in the high-voltage device region serves as a drift region for fabricating the high-voltage device. Therefore, one mask is used to define a ...	04/10/2001
6211555	Semiconductor device with a pair of transistors having dual work function gate electrodes Techniques are described for fabricating a pair of ଲ-identical transistors, in other words, a pair of transistors whose dimensions and electrical characteristics, other than their respective gate electrode work functions, are substantially similar. ...	04/03/2001
6194776	Semiconductor circuit device having triple-well structure in semiconductor substrate, method of fabricating the same, and mask device for fabrication of the same A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well reg...	02/27/2001
6194766	Integrated circuit having low voltage and high voltage devices on a common semiconductor substrate High voltage and low voltage devices are provided on a common semiconductor substrate. An integrated semiconductor circuit includes a semiconductor substrate of a first conductivity type. Well regions of a first conductivity type and well regions of a sec...	02/27/2001
6187637	Method for increasing isolation ability using shallow trench A method for increasing isolation ability is disclosed. A shallow trench into semiconductor device is formed on a wafer. Therefore the wafer owns a semiconductor substrate and wherein a first gate oxide layer is formed on the semiconductor substrate. A ni...	02/13/2001
6166415	Semiconductor device with improved noise resistivity A dummy pattern that is inserted to stabilize the form of a transistor active region is implanted with an impurity of the same conductivity type as a well, and the impurity-doped region of the dummy pattern is supplied with a potential through a metal int...	12/26/2000

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Class 257/E21.63 - With particular manufacturing method of wells or tubs, e.g., twin tubs, high energy well implants, buried implanted layers for lateral isolation (BILLI) (EPO)