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| Number | Title | Issue Date |
| 7435628 | Method of forming a vertical MOS transistor A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. Th... | 10/14/2008 |
| 7432160 | Semiconductor devices including transistors having three dimensional channels and methods of fabricating the same Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional struct... | 10/07/2008 |
| 7432162 | Semiconductor device with substantial driving current and decreased junction leakage current The semiconductor device includes an active region, a stepped recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate.... | 10/07/2008 |
| 7420230 | MOSFET-type semiconductor device, and method of manufacturing the same A MOSFET-type semiconductor device includes a monocrystalline semiconductor layer formed in a shape of a thin wall on a insulating film, a gate electrode straddling over the semiconductor layer around the middle portion of the wall-shaped semiconductor layer via a g... | 09/02/2008 |
| 7413954 | Insulated gate semiconductor device and manufacturing method of the same A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped pol... | 08/19/2008 |
| 7410856 | Methods of forming vertical transistors A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars, forming... | 08/12/2008 |
| 7368353 | Trench power MOSFET with reduced gate resistance A method for manufacturing a trench type power semiconductor device which includes process steps for forming proud gate electrodes in order to decrease the resistivity thereof. ... | 05/06/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7348243 | Semiconductor device and method for fabricating the same A transistor and a method for fabricating the same is disclosed, to uniformly provide impurity ions in impurity areas, and to prevent a short channel effect, in which the method for fabricating the transistor includes steps of forming a plurality of channel ion impl... | 03/25/2008 |
| 7339239 | Vertical NROM NAND flash memory array Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of the present invention include NROM memory cells in high density vert... | 03/04/2008 |
| 7335565 | Metal-oxide-semiconductor device having improved performance and reliability A method for forming a MOS device includes the steps of forming a gate proximate an upper surface of a semiconductor layer, the semiconductor layer including a substrate of a first conductivity type and a second layer of a second conductivity type; forming first and... | 02/26/2008 |
| 7332369 | Organic electronic devices A method for forming an organic electronic device, which method comprises the steps of: a) forming a negative image of a desired pattern on a substrate or device layer with a lift-off ink; b) coating a first device... | 02/19/2008 |
| 7332398 | Manufacture of trench-gate semiconductor devices A method of manufacturing a trench-gate semiconductor device (1), the method including forming trenches (20) in a semiconductor body (10) in an active transistor cell area of the device, the trenches (20) each having a trench bottom and t... | 02/19/2008 |
| 7326621 | Method of fabricating a recess channel array transistor using a mask layer with a high etch selectivity with respect to a silicon substrate A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After formin... | 02/05/2008 |
| 7326611 | DRAM arrays, vertical transistor structures and methods of forming transistor structures and DRAM arrays The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars... | 02/05/2008 |
| 7319060 | Semiconductor device and method of manufacturing the semiconductor device A semiconductor device includes a pair of first source/drain regions disposed on a silicon substrate. A first silicon epitaxial layer pattern defines a gate forming region that exposes the silicon substrate between the pair of first source/drain regions. A first gat... | 01/15/2008 |
| 7288815 | Semiconductor device and manufacturing method thereof A semiconductor device (20, 21, 22), including: a channel region (4) of a first conductivity type formed at a surface layer portion of a semiconductor substrate (1); a source region (25) of a second conductivity type which is different fr... | 10/30/2007 |
| 7271048 | Method for manufacturing trench MOSFET A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is f... | 09/18/2007 |
| 7242040 | Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making, and integrated circuits incorporating the transistors A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel,... | 07/10/2007 |
| 7229872 | Low voltage power MOSFET device and process for its manufacture A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capaci... | 06/12/2007 |
| 7220644 | Single-pole component manufacturing The invention relates to a vertical-type single-pole component, comprising regions with a first type of conductivity which are embedded in a thick layer with a second type of conductivity. Said regions are distributed over at least one same horizontal level and are ... | 05/22/2007 |
| 7193912 | Semiconductor integrated circuit device A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a com... | 03/20/2007 |
| 7132321 | Vertical conducting power semiconductor devices implemented by deep etch Semiconductor substrates suitable for making thin vertical current conducting devices are made by providing a relatively thick semiconducting substrate with at least one conductivity type having a thickness of from about 100 μm to 700 μm. At least one active devic... | 11/07/2006 |
| 7115476 | Semiconductor manufacturing method and semiconductor device A method of manufacturing a semiconductor device includes forming a mask layer on a semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a semiconductor pillar, doping an impurity into the semiconductor substra... | 10/03/2006 |
| 6855606 | Semiconductor nano-rod devices In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of th... | 02/15/2005 |
| 6690040 | Vertical replacement-gate junction field-effect transistor A vertical JFET architecture. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of differ... | 02/10/2004 |
| 6686604 | Multiple operating voltage vertical replacement-gate (VRG) transistor An architecture for creating multiple operating voltage MOSFETs. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second spaced-apart doped regions formed in the surface. A th... | 02/03/2004 |
| 6683363 | Trench structure for semiconductor devices A MOS trench structure integrated with a semiconductor device for enhancing the breakdown characteristics of the semiconductor device, comprises a semiconductor substrate, a plurality of parallel trenches formed in the semiconductor substrate, a periphera... | 01/27/2004 |
| 6677205 | Integrated spacer for gate/source/drain isolation in a vertical array structure Alignment tolerance for a vertical gate transistor device can be relaxed because of a spacer formed adjacent the trench. The gate electrode is formed of two materials that have etch selectivity between them, such that the outer material can be etched a pr... | 01/13/2004 |
| 6649476 | Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array A monotonic dynamic-static pseudo-NMOS logic circuit comprises a dynamic logic circuit having a clock input and having an output configured to be pre-charged high when a low clock signal is provided to the clock input; and a static logic circuit having a ... | 11/18/2003 |
| 6649479 | Method for fabricating MOSFET device A MOSFET device includes a gate formed on a multi-surface area of a semiconductor substrate formed of a first surface which is not etched, a second surface etched in parallel with the first surface, and a surface connecting the first and second surfaces. ... | 11/18/2003 |
| 6645815 | Method for forming trench MOSFET device with low parasitic resistance A method is provided for forming shallow and deep dopant implants adjacent source regions of a first conductivity type within an upper portion of an epitaxial layer in a trench MOSFET device. The method comprises: (a) forming a patterned implantation mask... | 11/11/2003 |
| 6639275 | Semiconductor device with vertical MOSFET A semiconductor device improves the gate withstand voltage of vertical MOSFETs and raises their operation speed. The gate electrode is formed in the trench of the second semiconductor layer. The interlayer dielectric layer has the contact hole that expose... | 10/28/2003 |
| 6635924 | Ultra thin body vertical replacement gate MOSFET A method of fabricating a VRG MOSFET includes the steps of: (a) forming a VRG multilayer stack; (b) forming a trench in the stack; (c) depositing an ultra thin, amorphous semiconductor (-semic) layer on the sidewalls of the trench (portions of the ... | 10/21/2003 |
| 6635534 | Method of manufacturing a trench MOSFET using selective growth epitaxy A method of manufacturing a trench structure for a trench MOSFET, including the steps of providing a semiconductor substrate having a major surface, forming a dielectric pillar on the substrate major surface (the dielectric pillar extending substantially ... | 10/21/2003 |
| 6621121 | Vertical MOSFETs having trench-based gate electrodes within deeper trench-based source electrodes Vertical MOSFETs include a semiconductor substrate having a plurality of semiconductor mesas therein that are separated by a plurality of deep stripe-shaped trenches. These stripe-shaped trenches extend in parallel and lengthwise across the substrate in a... | 09/16/2003 |
| 6621118 | MOSFET, semiconductor device using the same and production process therefor A MOSFET includes: a first conductivity type a semiconductor substrate having a trench formed in a surface area thereof, a gate electrode formed on the semiconductor substrate; and a trench gate electrode which is adjacent to the gate electrode and is bur... | 09/16/2003 |
| 6576954 | Trench MOSFET formed using selective epitaxial growth A method of creating a thermally grown oxide of any thickness at the bottom of a silicon trench. A dielectric (e.g. oxide) pillar of a predetermined thickness is formed on a semiconductor substrate. A selective epitaxial growth (SEG) process is used to fo... | 06/10/2003 |
| 6570208 | 6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. ... | 05/27/2003 |
| 6548872 | Integrated circuitry comprising multiple transistors with different channel lengths A method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global outer surface extending along a plane. First and second openin... | 04/15/2003 |
